Pulse width modulation converter

ABSTRACT

A PWM converter includes a power source current detector (9), current instruction generator (7), current controller (6) and a main circuit power control section (8), and the current controller is constituted of comparators (17, 18, 19) which compare the line current measurement results with the line current instruction values, and a logic circuit (10) which generates switching instruction signals (PU, PV, PW) based on the comparison results with use of timing signals so that the switching power devices (Q1-Q6) are selectively turned ON and OFF in the direction of reducing the difference between the line current measurement results and the line current instruction values, and thus essentially solves the prior art problems associated with gain adjustment of current error amplifiers, which is completely adjustment-free and yet inexpensive.

TECHNOLOGICAL FIELD

The present invention relates to a pulse width modulation converter(referred to as "PWM converter" hereinafter), in particular to a PWMconverter for converting three-phase AC power to DC power.

BACKGROUND ART

In recent years, PWM converters have been widely used with an object oftransmitting and receiving electric power in both directions from an ACpower source to a DC power source or from a DC power source to an ACpower source.

PWM converters are also often used with an object of reducing a phasedifference of voltage and current of an AC power source, i.e., for thepurpose of improving a power factor, and suppressing current distortionof an AC power source, i.e., reducing higher harmonics of the powersource.

A typical conventional PWM converter system will now be described withreference to FIGS. 14 to 17.

In FIG. 14, it is assumed that a voltage between a plus terminal and aminus terminal of a smoothing capacitor 60 is higher than the maximumvalue of a phase voltage of a three-phase AC power source 1. First ofall, in a current instruction generator 7, a phase information value θand amplitude instruction value ip of the three-phase AC current waveform to be supplied from the three-phase AC power source 1 are set, andon the basis of these values of information, the current instructiongenerator 7 generates respective line current instructions that are tobe input from the three-phase AC power source 1: these are first linecurrent instruction iTU, second line current instruction iTV, and thirdline current instruction iTW.

Next, a power source current detector 9 detects two line currents of thethree line currents output from the three-phase AC power source 1 andthe remaining one line current is then obtained by taking the sum of thetwo detected line currents and inverting the sign thereof, and theobtained three line currents are output as the first line currentmeasurement result iFU, second line current measurement result iFV, andthird line current measurement result iFW. It should be noted here thatthis power source current detector 9 may be also constructed to detectthe three line currents of the three-phase AC power source 1, outputtingthese as first line current measurement result iFU, second line currentmeasurement result iFV and third line current measurement result iFW.

Next, a current controller 106 receives these first line currentinstruction iTU, second line current instruction iTV, third line currentinstruction iTW, and first line current measurement result iFU, secondline current measurement result iFV, and third line current measurementresult iFW to be compared, respectively, and generates a first switchinginstruction signal PU, second switching instruction signal PV, and thirdswitching instruction signal PW controlling such that, the first linecurrent instruction iTU and first line current measurement result iFU,the second line current instruction iTV and second line currentmeasurement result iFV, and the third line current instruction iTW andthird line current measurement result iFW are respectively coincidentwith each other as closely as possible.

Next, a main circuit power control section 8 includes the smoothingcapacitor 60 and a switching power device group having a three-phasebridge construction. The switching power device group is comprised of afirst switching power device Q1 connected to the plus terminal of thesmoothing capacitor 60 for controlling the first line current IU, secondswitching power device Q2 connected to the plus terminal of thesmoothing capacitor 60 for controlling the second line current IV, thirdswitching power device Q3 connected to the plus terminal of thesmoothing capacitor 60 for controlling the third line current IW, fourthswitching power device Q4 connected to the minus terminal of thesmoothing capacitor 60 for supplying the first line current IU to thethree-phase AC power source 1, fifth switching power device Q5 connectedto the minus terminal of the smoothing capacitor 60 for controlling thesecond line current IV, sixth switching power device Q6 connected to theminus terminal of the smoothing capacitor 60 for controlling the thirdline current IW, where each switching power device has a reflux diodeconnected in parallel thereto.

By this construction, any one of the first switching power device Q1 andfourth switching power device Q4 is turned ON in response to the firstswitching instruction signal PU, any one of the second switching powerdevice Q2 and fifth switching power device Q5 is turned ON in responseto the second switching instruction signal PV, and any one of the thirdswitching power device Q3 and sixth switching power device Q6 is turnedON in response to the third switching instruction signal PW.

The description is now given assuming an arrangement such that, when thefirst switching instruction signal PU is L level, the first switchingpower device Q1 is turned ON, while when the first switching instructionsignal PU is H level, the fourth switching power device Q4 is turned ON,and when the second switching instruction signal PV is L level, thesecond switching power device Q2 is turned ON, while when the secondswitching instruction signal PV is H level, the fifth switching powerdevice Q5 is turned ON, and when the third switching instruction signalPW is L level, the third power switching device Q3 is turned ON, whilewhen the third switching instruction signal PW is H level, the sixthswitching power device Q6 is turned ON.

In the case where the voltage between the plus terminal and minusterminal of the smoothing capacitor 60 gets below the maximum value ofthe phase voltage of the three-phase AC power source 1, the three-phaseAC voltage is rectified by the reflux diodes of the switching powerdevice group Q1 to Q6.

FIG. 15 shows a conventional construction of the current controller 106included in the conventional PWM converter system shown in FIG. 14.Also, FIGS. 16A to 16E show an operation of FIG. 15.

In the current controller 106, the first, second and third line currentinstructions iTU, iTV, iTW and the first, second and third line currentmeasurement results iFU, iFV, iFW are respectively subtracted by meansof subtraction units 117, 118 and 119 so as to obtain first, second andthird line current error signals iEU, iEV and iEW. The first, second andthird line current error signals iEU, iEV and iEW are input to first,second and third current error amplifiers 120, 121, 122 respectively tooutput first, second and third voltage instruction signals VU, VV and VWto be fed to a three-phase PWM signal generator section 139. For each ofthe current error amplifiers 120 to 122, a PI type(proportional/integral type) amplifier is typically employed as shown inFIG. 17, and its gain characteristic is obtained by the followingequation:

    G=R2×(R3×C1×S)/[R1×{(R2+R3)×C1×S+1}]

The three-phase PWM signal generator section 139 includes first, secondand third comparators 123, 124 and 125 and a triangular wave generator126 generating a triangular wave signal SC to be input to minusterminals of the first, second and third comparators 123, 124 and 125.The first, second and third comparators 123, 124 and 125 receives thefirst, second and third voltage instruction signals W, VV and VW attheir plus input terminals and compare the respective voltageinstruction signals W, VV, and VW with the triangular wave signal SC, tothereby generate the first, second and third switching instructionsignals PU, PV and PW.

In this construction, it is assumed that, when the voltage instructionsignals W, VV and VW are respectively larger than the triangular wavesignal SC, the first, second and third comparators 123, 124 and 125generate H level, and in the meanwhile, when smaller, the comparatorsgenerate L level.

FIGS. 16A to 16E show the operation of the current controller 106 shownin FIG. 15, noting here that the operation is shown for the case wherethe first, second and third line current instructions iTU, iTV and iTWare three-phase sine waves.

In FIG. 15 and FIGS. 16A to 16E, in considering the gain of the currenterror amplifiers 120 to 122, it can be seen that, the larger the gain ofthe current error amplifiers, the nearer the line current instructionsand line current measurement results approach each other and the linecurrent errors can be made small, improving the response characteristicof the line current measurement results with respect to the line currentinstructions.

However, with the above conventional construction, due, for example, tophase lag produced by reactors 59, phase lag of the current erroramplifiers, and dead time delay in the three-phase PWM signal generatorsection 139, if the gain of the current error amplifiers is made toolarge, oscillation phenomenon occurs. Therefore, normally chosen is avalue of the current error amplifier gain as large as possible in arange such that oscillation does not occur. This gain value of eachcurrent error amplifier is determined at the design stage by studyingthe loop transfer function of the current control loop from theviewpoint of the characteristics of the three-phase AC power source 1,reactors 59, power source current detector 9, current controller 8 andmain circuit power control section 8. In determination of the gain, itis necessary to lower the gain to a degree where oscillation does notoccur even in the worst case, taking into account manufacturingvariation of these characteristics and temperature characteristics. Thetask of determining this gain requires a lot of effort in design andon-site and requires considerable efforts in management in manufactureand on-site.

Also, since the optimum gain of the current error amplifiers changesdepending on the DC voltage, a system must be constructed in which thegain is variable.

Next, there is a problem that, because the offset and/or drift of thetriangular wave generator and the current error amplifier per se have anadverse effect on the current control error and/or restrict the range ofdynamic drift, operational amplifiers are required such that the offsetand drift of these components are small, and in some cases an offsetadjustment operation is necessary during a manufacture process, whichincreases costs.

It should be noted that, although FIG. 15 is a conventional example inwhich the current controller 106 is implemented by analogue circuitry,the first, second and third line current measurement results iFU, iFV,iFW can be converted to digital data and the same constitution can beimplemented by digital circuitry such as a microcomputer. Even in thiscase, the gain of the current error amplifiers must be determined bystudying the loop transfer function of the current control loop in viewof the characteristics of the three-phase AC power source, power sourcecurrent detector, current controller and main circuit power controlsection, and this task is the same as in the case of implementation byanalogue circuitry.

Furthermore, when the current error amplifiers are implemented usingdigital circuitry such as a microcomputer, since the offset and drift ofthe current error amplifiers themselves are digital calculations, theycan be eliminated. However, phase lag gets larger as such calculationprocessing time increases and this tends to facilitate oscillation. Thisresults in the problem that gain can not be increased without making theprocessing time very short, necessitating the use of a microcomputer orthe like of very fast calculation processing capability, which isexpensive undesirably.

Also regarding the A/D converter for converting the first, second andthird line current measurement results iFU, iFV, iFW to digital data,phase lag increases as the conversion time gets longer, whichfacilitates to cause oscillation. This results in that the gain couldnot be increased without making the conversion time very short,necessitating the use of an A/D converter of very fast conversioncapability, which is expensive. Also, offset and drift in the A/Dconversion adversely affect the current control error and restrict thedynamic range, and therefore an A/D converter must be selected to havevery small offset and drift, resulting in the problem of high cost.

DISCLOSURE OF INVENTION

Therefore, the present invention has been developed to solve theproblems inherent to the conventional system, and an essential objectthereof is to provide a PWM converter of low cost, without requirementof gain adjustment at all, having an excellent response characteristicof line current measurement results with respect to line currentinstructions.

In order to attain this object, according to a first aspect of thepresent invention, a PWM converter comprises: a power source currentdetector for detecting first, second and third line currents of athree-phase AC power source and generating first, second and third linecurrent measurement results; a current instruction generator forgenerating first, second and third line current instruction values; amain circuit power control section which includes switching power meansfor controlling the first, second and third line currents; and a currentcontroller which includes first, second and third comparators comparingthe first, second and third line current measurement results with thefirst, second and third line current instruction values respectively tooutput first, second and third line current comparison results, and alogic circuit generating first, second and third switching instructionsignals based on the first, second and third line current comparisonresults to switch the switching power means on and off in a manner suchthat the first, second and third line current measurement resultscoincide as closely with the first, second and third line currentinstruction values, respectively.

In this arrangement, the current controller further includes a timingsignal generator generating a periodic state update timing signal to beapplied to the logic circuit so that the logic circuit determines thelevels of the switching instruction signals for putting the switchingpower means on and off at the timing of change in the line currentcomparison results in accordance with the state update timing signal.

The first, second and third comparators output the line currentcomparison results of a first level when the first, second and thirdline current measurement results are larger than the first, second andthird line current instruction values, respectively, and output the linecurrent comparison results of a second level when the first, second andthird line current measurement results are smaller than the first,second and third line current instruction values, respectively, andwherein said switching power means is comprised of first, second, third,fourth, fifth and sixth switching power devices, so that the logiccircuit determines the levels of the switching instruction signals forputting the first, second, third, fourth, fifth and sixth switchingpower devices in the on and off conditions, respectively.

By this arrangement, by repeating a simple operation of determining therespective ON or OFF condition of the first, second, third, fourth,fifth and sixth switching power devices in a direction of reducing thedifference between the respective line current instructions and linecurrent measurement results at the timing of changing the first, secondand third line current comparison results and at the state updatetiming, the line currents of the three-phase AC power source can be madeto approach the respective line current instruction signals andtherefore the line current errors can thereby be reduced.

With the PWM converter of the present invention, the construction has nocurrent error amplifier provided, so the problems involved in gainadjustment of a current error amplifier can be essentially solved and nogain adjustment is necessary at all.

Furthermore, even if there are changes in the characteristics andspecification of the three-phase AC power source, power source currentdetector, current controller, or main circuit power control section, theline current errors are always made minimum, and even in the presence ofmanufacturing variation of performance and temperature characteristicsetc., the line current errors can be always made minimum so that currentcontrol response can be made excellent and there is no risk ofoscillation.

Also, except for the first, second and third comparator means, thecurrent controller in the PWM converter according to the presentinvention can be constructed entirely of simple digital circuitry, andthus the portion constructed of digital circuitry has no risk of offsetor drift, with reduction in cost.

According to a second aspect of the present invention, the logic circuitis adapted to determine the switching instruction signals such that,

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a second level and the third line current comparison result is ofa second level, the second, third and fourth switching power devices areswitched to the off condition while the first, fifth and sixth switchingpower devices are switched to the on condition, and then in thesubsequent period from the time-point where the second line currentcomparison result becomes of a first level up to a time-point of thenext state update timing, the fifth switching power device is switchedto the off condition while the second switching power device is switchedto the on condition, and then in the subsequent period from thetimepoint where the third line current comparison result becomes of afirst level up to a time-point of the next state update timing, thesixth switching power device is switched to the off condition while thethird switching power device is switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a first level and the third line current comparison resultis of a second level, the first, third and fifth switching power devicesare switched to the off condition while the second, fourth and sixthswitching power devices are switched to the on condition, and then inthe subsequent period from the time-point where the first line currentcomparison result becomes of a first level up to a time-point of thenext state update timing, the fourth switching power device is switchedto the off condition while the first switching power device is switchedto the on condition, and then in the subsequent period from thetime-point where the third line current comparison result becomes of afirst level up to a time-point of the next state update timing, thesixth switching power device is switched to the off condition while thethird switching power device is switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a second level and the third line current comparison resultis of a first level, the first, second and sixth switching power devicesare switched to the off condition while the third, fourth and fifthswitching power devices are switched to the on condition, and then inthe subsequent period from the time-point where the first line currentcomparison result becomes of a first level up to a time-point of thenext state update timing, the fourth switching power device is switchedto the off condition while the first switching power device is switchedto the on condition, and then in the subsequent period from thetimepoint where the second line current comparison result becomes of afirst level up to a time-point of the next state update timing, thefifth switching power device is switched to the off condition while thesecond switching power device is switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a first level and the third line current comparison resultis of a first level, the first, fifth and sixth switching power devicesare switched to the off condition while the second, third and fourthswitching power devices are switched to the on condition, and then inthe subsequent period from the time-point where the second line currentcomparison result becomes of a second level up to a time-point of thenext state update timing, the second switching power device is switchedto the off condition while the fifth switching power device is switchedto the on condition, and then in the subsequent period from thetime-point where the third line current comparison result becomes of asecond level up to a time-point of the next state update timing, thethird switching power device is switched to the off condition while thesixth switching power device is switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a second level and the third line current comparison result is ofa first level, the second, fourth and sixth switching power devices areswitched to the off condition while the first, third and fifth switchingpower devices are switched to the on condition, and then in thesubsequent period from the time-point where the first line currentcomparison result becomes of a second level up to a time-point of thenext state update timing, the first switching power device is switchedto the off condition while the fourth switching power device is switchedto the on condition, and then in the subsequent period from thetime-point where the third line current comparison result becomes of asecond level up to a time-point of the next state update timing, thethird switching power device is switched to the off condition while thesixth switching power device is switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a first level and the third line current comparison result is of asecond level, the third, fourth and fifth switching power devices areswitched to the off condition while the first, second and sixthswitching power devices are switched to the on condition, and then inthe subsequent period from the time-point where the first line currentcomparison result becomes of a second level up to a time-point of thenext state update timing, the first switching power device is switchedto the off condition while the fourth switching power device is switchedto the on condition, and then in the subsequent period from thetime-point where the second line current comparison result becomes of asecond level up to a time-point of the next state update timing, thesecond switching power device is switched to the off condition while thefifth switching power device is switched to the on condition.

According to a third aspect of the present invention, the logic circuitis adapted to determine the switching instruction signals such that,

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a second level and the third line current comparison result is ofa second level, the second, third and fourth switching power devices areswitched to the off condition while the first, fifth and sixth switchingpower devices are switched to the on condition, and when the second linecurrent comparison result becomes of a first level prior to the thirdline current comparison result, the fifth switching power device isswitched to the off condition while the second switching power device isswitched to the on condition which the conditions remain up to atimepoint where the third line current comparison result becomes of afirst level, and then in the subsequent period from the time-point wherethe third line current comparison result becomes of a first level up toa time-point of the next state update timing, the first, second andthird switching power devices are switched to the off condition whilethe fourth, fifth and sixth switching power devices are switched to theon condition, whereas when the third line current comparison resultbecomes of a first level prior to the second line current comparisonresult, the sixth switching power device is switched to the offcondition while the third switching power device is switched to the oncondition which the conditions remain up to a time-point where thesecond line current comparison result becomes of a first level, and thenin the subsequent period from the time-point where the second linecurrent comparison result becomes of a first level up to a time-point ofthe next state update timing, the first, second and third switchingpower devices are switched to the off condition while the fourth, fifthand sixth switching power devices are switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a first level and the third line current comparison resultis of a second level, the first, third and fifth switching power devicesare switched to the off condition while the second, fourth and sixthswitching power devices are switched to the on condition, and when thethird line current comparison result becomes of a first level prior tothe first line current comparison result, the sixth switching powerdevice is switched to the off condition while the third switching powerdevice is switched to the on condition which the conditions remain up toa time-point where the first line current comparison result becomes of afirst level, and then in the subsequent period from the time-point wherethe first line current comparison result becomes of a first level up toa time-point of the next state update timing, the first, second andthird switching power devices are switched to the off condition whilethe fourth, fifth and sixth switching power devices are switched to theon condition, whereas when the first line current comparison resultbecomes of a first level prior to the third line current comparisonresult, the fourth switching power device is switched to the offcondition while the first switching power device is switched to the oncondition which the conditions remain up to a time-point where the thirdline current comparison result becomes of a first level, and then in thesubsequent period from the time-point where the third line currentcomparison result becomes of a first level up to a time-point of thenext state update timing, the first, second and third switching powerdevices are switched to the off condition while the fourth, fifth andsixth switching power devices are switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a second level and the third line current comparison resultis of a first level, the first, second and sixth switching power devicesare switched to the off condition while the third, fourth and fifthswitching power devices are switched to the on condition, and when thefirst line current comparison result becomes of a first level prior tothe second line current comparison result, the fourth switching powerdevice is switched to the off condition while the first switching powerdevice is switched to the on condition which the conditions remain up toa time-point where the second line current comparison result becomes ofa first level, and then in the subsequent period from the time-pointwhere the second line current comparison result becomes of a first levelup to a time-point of the next state update timing, the first, secondand third switching power devices are switched to the off conditionwhile the fourth, fifth and sixth switching power devices are switchedto the on condition, whereas when the second line current comparisonresult becomes of a first level prior to the first line currentcomparison result, the fifth switching power device is switched to theoff condition while the second switching power device is switched to theon condition which the conditions remain up to a time-point where thefirst line current comparison result becomes of a first level, and thenin the subsequent period from the time-point where the first linecurrent comparison result becomes of a first level up to a time-point ofthe next state update timing, the first, second and third switchingpower devices are switched to the off condition while the fourth, fifthand sixth switching power devices are switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a second level and the second line current comparisonresult is of a first level and the third line current comparison resultis of a first level, the first, fifth and sixth switching power devicesare switched to the off condition while the second, third and fourthswitching power devices are switched to the on condition, and when thesecond line current comparison result becomes of a second level prior tothe third line current comparison result, the second switching powerdevice is switched to the off condition while the fifth switching powerdevice is switched to the on condition which the conditions remain up toa time-point where the third line current comparison result becomes of asecond level, and then in the subsequent period from the time-pointwhere the third line current comparison result becomes of a second levelup to a time-point of the next state update timing, the fourth, fifthand sixth switching power devices are switched to the off conditionwhile the first, second and third switching power devices are switchedto the on condition, whereas when the third line current comparisonresult becomes of a second level prior to the second line currentcomparison result, the third switching power device is switched to theoff condition while the sixth switching power device is switched to theon condition which the conditions remain up to a time-point where thesecond line current comparison result becomes of a second level, andthen in the subsequent period from the time-point where the second linecurrent comparison result becomes of a second level up to a time-pointof the next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a second level and the third line current comparison result is ofa first level, the second, fourth and sixth switching power devices areswitched to the off condition while the first, third and fifth switchingpower devices are switched to the on condition, and when the third linecurrent comparison result becomes of a second level prior to the firstline current comparison result, the third switching power device isswitched to the off condition while the sixth switching power device isswitched to the on condition which the conditions remain up to atime-point where the first line current comparison result becomes of asecond level, and then in the subsequent period from the time-pointwhere the first line current comparison result becomes of a second levelup to a time-point of the next state update timing, the fourth, fifthand sixth switching power devices are switched to the off conditionwhile the first, second and third switching power devices are switchedto the on condition, whereas when the first line current comparisonresult becomes of a second level prior to the third line currentcomparison result, the first switching power device is switched to theoff condition while the fourth switching power device is switched to theon condition which the conditions remain up to a time-point where thethird line current comparison result becomes of a second level, and thenin the subsequent period from the time-point where the third linecurrent comparison result becomes of a second level up to a time-pointof the next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition; and

at said state update timing, when the first line current comparisonresult is of a first level and the second line current comparison resultis of a first level and the third line current comparison result is of asecond level, the third, fourth and fifth switching power devices areswitched to the off condition while the first, second and sixthswitching power devices are switched to the on condition, and when thesecond line current comparison result becomes of a second level prior tothe first line current comparison result, the second switching powerdevice is switched to the off condition while the fifth switching powerdevice is switched to the on condition which the conditions remain up toa time-point when the first line current comparison result becomes of asecond level, and then in the subsequent period from the time-pointwhere the first line current comparison result becomes of a second levelup to a time-point of the next state update timing, the fourth, fifthand sixth switching power devices are switched to the off conditionwhile the first, second and third switching power devices are switchedto the on condition, whereas when the first line current comparisonresult becomes of a second level prior to the second line currentcomparison result, the first switching power device is switched to theoff condition while the fourth switching power device is switched to theon condition which the conditions remain up to a time-point where thesecond line current comparison result becomes of a second level, andthen in the subsequent period from the time-point where the second linecurrent comparison result becomes of a second level up to a time-pointof the next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition.

According to a fourth aspect of the present invention, the first, secondand third comparators are adapted to periodically compare the first,second and third line current instruction values with the first, secondand third line current measurement results, respectively, and thecurrent controller further comprises first, second and thirddouble-reading logic circuits respectively interconnected between thefirst, second and third comparators and the logic circuit adapted suchthat, in the case where the first, second and third line currentmeasurement results are greater than the first, second and third linecurrent instruction values at least successive two times, respectively,the first, second and third comparators output the first, second andthird line current comparison results of a first level, and whereas, inthe case where the first, second and third line current measurementresults are smaller than the first, second and third line currentinstruction values at least successive two times, respectively, thefirst, second and third comparators output the first, second and thirdline current comparison results of a second level, respectively.

By this arrangement, noise superimposed on the output signals of thecomparator means can be removed and even under conditions that aresubject to noise generation, the line currents of the three-phase ACpower source can be controlled to coincide accurately with the first,second and third line current instructions.

According to a fifth aspect of the present invention, the logic circuitfurther includes first, second and third delay units for delayingswitching instruction signals by predetermined times in accordance witha predetermined rule to be fed to the main circuit power controlsection.

By this arrangement, the delay means output switching instructionsignals of the first, second, third, fourth, fifth and sixth switchingpower devices to be delayed by a predetermined time at the timing ofchanging the first, second and third line current comparison results,the line currents of the three-phase AC power source can be made tocoincide very closely with the line current instructions.

According to a sixth aspect of the present invention, the currentinstruction generator generates the first, second and third line currentinstruction signals, each consisting of a sine wave of in-phase or asine wave of anti-phase with respect to each phase voltage, seen fromthe neutral point of the three-phase AC power source.

By this arrangement, a reduction in the phase difference between thephase voltages and the line currents i.e. improvement in the powerfactor can be achieved and since each line current can be controlled toa sine wave, distortion of the line currents can be suppressed i.e.higher harmonics of the power source can be reduced.

Thus, it can be seen that, in the PWM converter according to the presentinvention, by repetition of a simple operation in which the respectiveON or OFF condition of the first, second, third, fourth, fifth and sixthmain circuit switching power devices is determined in such a directionas to decrease the difference between the respective line currentinstructions and line current measurement results at the timing ofchanging the first, second and third line current comparison results andat the state update timing, the line currents of the three-phase ACpower source can be made to approach the respective line currentinstruction signals and the line current errors can thereby be reduced.with the PWM converter of the present invention, the construction has nocurrent error amplifier provided, so the problems involved in gainadjustment of a current error amplifier can be essentially solved and nogain adjustment is con necessary at all.

Furthermore, even if the characteristics and specification of the reactors, power source current detector, current controller or maincircuit power control section are changed, the line current errors arealways kept to be the minimum, and even if there is manufacturingvariation of the characteristics or temperature characteristics etc.,the line current errors are always kept to the minimum, and thereforeexcellent current control response can be provided and there is no riskof oscillation.

Also, even if the DC voltage changes, there is no need to adjust thegain and operation is always performed to keep the line current errorsminimum.

Also, except for the first, second and third comparator means, thecurrent controller in a PWM converter according to the present inventioncan be constructed entirely of simple digital circuitry, and there forethe portion constructed of digital circuitry has no risk of offset ordrift and is of low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a PWM converter according to the presentinvention;

FIG. 2 is a block diagram of a current controller according to theembodiment of FIG. 1;

FIG. 3 is a truth value table of a logic circuit used in the firstembodiment of the present invention;

FIG. 4 is a block diagram of a logic circuit of the first embodiment;

FIG. 5 is a timing chart of a timing signal distributing unit in thelogic circuit of FIG. 2;

FIGS. 6A, 6B and 6C are explanatory views given in explanation of theoperation of FIG. 1 and FIG. 2;

FIG. 7 is a circuit diagram showing a construction is of a comparatorunit shown in FIG. 2;

FIG. 8 is a block diagram of a logic circuit according to a secondembodiment of the present invention;

FIG. 9 is a truth value table of a logic circuit used in the secondembodiment of the present invention;

FIG. 10 is a block diagram of a current controller according to a thirdembodiment of the present invention;

FIG. 11 is a block diagram showing a construction of a double-readinglogic circuit of FIG. 10;

FIG. 12 is a block diagram of a logic circuit according to a fourthembodiment of the present invention;

FIGS. 13A, 13B and 13C are explanatory views showing the operation ofthe current controller and delay unit delaying a switching instructionsignal according to a fourth embodiment of the present invention;

FIG. 14 is a block diagram of a typical conventional PWM converter;

FIG. 15 is a block diagram of a conventional current controller of FIG.14;

FIGS. 16A, 16B, 16C, 16D and 16E are timing charts showing the operationof the conventional current controller; and

FIG. 17 is a circuit diagram of a conventional current error amplifier.

BEST MODE FOR CARRYING OUT THE INVENTION

It is noted that, in the present invention, since the basic structuresof the present embodiments are similar to that of the conventional one,like parts are designated by the same reference numerals throughout thedrawings.

Embodiments of the present invention are described below with referenceto the drawings.

(Embodiment 1)

FIG. 1 shows a construction of a PWM converter system according to afirst embodiment of the present invention. In FIG. 1, the PWM convertersystem includes a power source current detector 9 for detecting linecurrents output from a three-phase AC power source 1, a currentinstruction generator 7 for generating line current instructions to besupplied from the three-phase AC power source 1, and a currentcontroller 6 for comparing the line current instructions generated bythe current instruction generator 7 with the current detection resultssupplied from the power source current detector 9 to control a maincircuit power control section 8.

In the case where a voltage between a plus terminal and a minus terminalof a smoothing capacitor 60 included in the main circuit power controlsection 8 is higher than the maximum value of a phase voltage of thethree-phase AC power source 1, a phase information value θ and amplitudeinstruction value ip of the three-phase AC current waveform to besupplied from the three-phase AC power source 1 are set in the currentinstruction generator 7 and then, based on these values of information,the current instruction generator 7 generates line current instructionsto be supplied from the three-phase AC power source 1, i.e., as thefirst line current instruction iTU, second line current instruction iTV,and third line current instruction iTW, and these line currentinstructions are fed to the current controller 6.

The power source current detector 9 detects any two line currents of thethree line currents IU, IV and IW output from the three-phase AC powersource 1 and then the remaining one line current is obtained by takingthe sum of the detected two line currents and inverting the signthereof. Thus, the power source current detector 9 outputs thesedetected three line currents as the first line current measurementresult iFU, second line current measurement result iFV, and third linecurrent measurement result iFW. It should be noted here that the powersource current detector 9 may be so constructed as to detect the threeline currents of the three-phase AC power source 1 at the same timestage and to output these values as the first line current measurementresult iFU, second line current measurement result iFV, and third linecurrent measurement result iFW.

Next, the current controller 6 receives the first line currentinstruction iTU, second line current instruction iTV, and third linecurrent instruction iTW from the current instruction generator 7 and thefirst line current measurement result iFU, second line currentmeasurement result iFV, and third line current measurement result iFWfrom the current controller 6, to be compared therebetween,respectively, and then generates a first switching instruction signalPU, second switching instruction signal PV, and third switchinginstruction signal PW such that, the first line current instruction iTUcoincides with the first line current measurement result iFU, the secondline current instruction iTV coincides with the second line currentmeasurement result iFV, and the third line current instruction iTWcoincides with the third line current measurement result iFW,respectively, as closely as possible.

The operation of this current controller 6 will be described in detaillater.

Next, the main circuit power control section 8 having the smoothingcapacitor 60 further includes a main circuit switching power devicegroup having a three-phase bridge construction which is comprised of afirst switching power device Q1 having its collector connected to theplus terminal of the smoothing capacitor 60 for controlling the firstline current IU, a second switching power device Q2 having its collectorconnected to the plus terminal of the smoothing capacitor 60 forcontrolling the second line current IV, a third switching power deviceQ3 having its collector connected to the plus terminal of the smoothingcapacitor 60 for controlling the third line current IW, a fourthswitching power device Q4 having its emitter connected to the minusterminal of the smoothing capacitor 60 for supplying the first linecurrent IU to the three-phase AC power source 1, a fifth switching powerdevice Q5 having its emitter connected to the minus terminal of thesmoothing capacitor 60 for controlling the second line current IV, asixth switching power device Q6 having its emitter connected to theminus terminal of the smoothing capacitor 60 for controlling the thirdline current IW, where the switching power devices Q1 to Q6 have refluxdiode D1 to D6 connected in parallel therewith, respectively, and theemitters of the first to third switching power devices Q1 to Q3 arerespectively connected to the collectors of the fourth to sixthswitching power devices Q4 to Q6 in parallel.

The main circuit power control section 8 further includes a base drivesection 4 having base drive units 4a and a logic inversion section 5having logic inversion units 5a. Thus, the first, second and thirdswitching instruction signals PU, PV and PW are supplied from thecurrent controller 6 to the bases of the first, second and thirdswitching power devices Q1, Q2 and Q3, respectively, via the base drivesection 4, while the first, second and third switching instructionsignals PU, PV and PW are also supplied to the bases of the fourth,fifth and sixth switching power devices Q4, Q5 and Q6, respectively, viathe logic inversion section 5 and the base drive section 4.

By this arrangement, any one of the first switching power device Q1 andfourth switching power device Q4 is selectively turned ON in response tothe first switching instruction signal PU, any one of the secondswitching power device Q2 and fifth switching power device Q5 isselectively turned ON in response to the second switching instructionsignal PV, and any one of the third switching power device Q3 and sixthswitching power device Q6 is selectively turned ON in response to thethird switching instruction signal PW.

In this embodiment, the description is given assuming an arrangementsuch that, the first switching power device Q1 is turned ON when thefirst switching instruction signal PU is L level while the fourthswitching power device Q4 is turned ON when the first switchinginstruction signal PU is H level, and the second switching power deviceQ2 is turned ON when the second switching instruction signal PV is Llevel while the fifth switching power device Q5 is turned ON when thesecond switching instruction signal PV is H level, and the thirdswitching power device Q3 is turned ON when the third switchinginstruction signal PW is L level while the sixth switching power deviceQ6 is turned ON when the third switching instruction signal PW is Hlevel.

Meanwhile, in the case where the voltage between the plus terminal andminus terminal of the smoothing capacitor 60 gets below the maximumvalue of the phase voltage of the three-phase AC power source 1, thethree-phase AC voltage is rectified by the reflux diodes D1 to D6 of theswitching power device group in the main circuit power control section8.

FIG. 2 shows a schematic construction of the current controller 6included in the PWM converter according to the first embodiment of thepresent invention shown in FIG. 1.

In FIG. 2, reference numerals 17, 18 and 19 denote first, second andthird comparators which receive the first, second and third line currentinstructions iTU, iTV and iTW at their respective inverting inputterminals and receive the first, second and third line currentmeasurement results iFU, iFV, and iFW at their respective non-invertinginput terminals, so that the line current instructions and the linecurrent measurement results are respectively compared with each other,and then the comparators generate first, second and third line currentcomparison results HU, HV and HW which are applied to a logic circuit10.

For convenience, in the subsequent description, it is assumed that theline current comparison results HU, HV and HW are H level when the linecurrent measurement results are larger than the values of the linecurrent instructions while the line current comparison results are Llevel when the line current measurement results are smaller than thevalues of the line current instructions.

Then, the logic circuit 10 receives the first, second and third linecurrent comparison results HU, HV and HW from the comparators and alsoreceives a state update timing signal CLK10 and a system clock signalCLK1 from a timing signal generator 11 and then output the first, secondand third switching instruction signals PU, PV and PW for instructing ONor OFF of the switching power devices Q1, Q2, Q3, Q4, Q5 and Q6.

In this logic circuit 10, first of all, at a timing of a rising edge ofthe state update timing signal CLK10, the state update is performed inaccordance with the level of the first, second and third line currentcomparison results HU, HV and HW to thereby generate the first, secondand third switching instruction signals PU, PV and PW. Then, in responseto a change in signal level of the first, second and third line currentcomparison results HU, HV and HW, the first, second and third switchinginstruction signals PU, PV and PW are altered.

The truth value table of the logic circuit 10 is shown in FIG. 3 and theway of reading FIG. 3 is described below.

In FIG. 3, State No. (A00, AX1, AX2, A00, AY1, AY2, B00, BX1 . . . CLR)represents the input/output state of the logic circuit 10, where asymbol .Arrow-up bold. of the state update timing signal CLKIOrepresents a timing of a leading edge of the state update timing signalCLK10 while a symbol ♦ represents a stable H level or L level state.

A symbol * of the line current comparison results HU, HV and HWindicates DON'T CARE i.e. that the operation is not affected by whetherH level or L level, where H indicates H level and L indicates L level. Areset signal RESET, which is normally L level, is input to the logiccircuit 10 for initialization of the logic circuit 10, and when thereset signal is H level, the logic circuit 10 is immediatelyinitialized.

Next, the operation of the logic circuit 10 is described with referenceto FIG. 3. First of all, when the state update timing signal CLK10 rises(i.e., when the leading edge is input to the logic circuit 10), theinput/output state of the logic circuit 10 transits to one of the eightstates: state No. A00, B00, C00, D00, E00, F00, G00, H00, depending onthe levels of the first, second and third line current comparisonresults HU, HV and HW at this point.

Referring to the first place of the state No., there are eight branchesA˜H, and for convenience in description, the Arabic numerical symbols ofthe three places of the state No. will be called, from the left, thefirst place, the second place and the third place.

First, the case will be described when state transition takes place toany one of the states No. A00, B00, C00, D00, E00, F00.

When transition takes place to one of the above six states, looking attwo signals having the same signal level among the first, second andthird line current comparison results HU, HV and HW at a timing of arising edge of the state update timing signal CLK10, subsequentoperation is different depending on which one of these two signalshaving the same level is the first to change. That is, looking at thesecond place of the state No., there are two branches represented by Xand Y.

For example, in the case of a state No. A00, if the second line currentcomparison result HV is the first to change (H to L), a transition takesplace to a state No. AX1, and if the third line current comparisonresult HW is the first to change (H to L), a transition takes place to astate No. AY1. If subsequently, of the first, second and third linecurrent comparison results HU, HV and HW at the timing of the leadingedge of the state update timing signal CLK10, the remaining one changes,which was not the first to change, of the two signals of the same signallevel, a transition takes place to a state No. which has state 2 in thethird place, remaining the first place and second place same as before.

For example, from state No. AX1, transition takes place to state No.AX2, and if the state No. is AY1, transition takes place to state No.AY2. Thereafter, this state is held until the timing of the next risingedge of the state update timing signal CLK10.

Lastly, the transition to state No. G00 or H00 at the timing of therising edge of the state update timing signal CLK10 will be described.In these cases, this condition is held until the input of the nextrising edge of the state update timing signal CLK10 so that the levelsof first, second and third switching instruction signals PU, PV and PWcontinue to be output.

Hereinbelow the operation of the logic circuit 10 is described based onthe truth value table shown in FIG. 3.

First of all, the operation at a timing of the rising edge of the stateupdate timing signal CLK10 will be described.

The logic circuit 10 reads the signal levels of the first, second andthird line current comparison results HU, HV and HW at the timing of therising edge of the state update timing signal CLK10 and then determinesthe signal levels of the switching instructions PU, PV, PW to be outputfrom the logic circuit 10 such that the first, second and third linecurrent measurement results iFU, iFV, and iFW are changed at that timein such a direction as to draw near to the respective first, second andthird line current instructions iTU, iTV, and iTW, in other words, sucha direction that iFU, iFV, and iFW coincide with the line currentinstructions iTU, iTV, and iTW. This results in that the signal levelsof the switching instructions PU, PV, and PW are respectively thoseobtained by inverting the line current comparison results HU, HV and HW.For example, if HU is H level, PU is determined to be L level and if HUis L level, PU is determined to be H level. The same applies to PV andPW.

Next, the operation of the logic circuit 10 after a timing of a risingedge of the state update timing signal CLK10 to the next timing of thesubsequent rising edge of the state update timing signal CLK10 isdescribed below.

The operation during this period is determined by the levels of thethree signals HU, HV and HW at the timing of the rising edge of thestate update timing signal CLK10. Referring to the levels of these threesignals HU, HV and HW, the description will be made below in terms ofthe operation in the case where the level of one signal of the threesignals is different, namely: ##EQU1## and the operation in the casewhere all three signals are the same, namely: ##EQU2##

First, the following describes the operation in the case where the levelof one signal of the three signals HU, HV and HW at the timing of therising edge of the state update timing signal CLK10 is different fromthe other two signal levels.

As described before in connection with the line current measurementresults detected by the power source current detector 9, it isself-evident that, in the three line currents of the three-phase ACpower source 1, the sum of the value of two line currents out of thethree line currents with inverted polarity is equal to the value of theremaining one. In the logic circuit 10 according to the first embodimentof the present invention, in consideration of the two signals having thesame level of the three signals HU, HV, and HW at the timing of therising edge of the state update timing signal CLK10, the levels of theswitching instruction signals PU, PV and PW are determined so as toeffect ON/OFF control of the switching power devices that supply theline currents in respect of the two signals having the same level.

More specifically, first of all, the level of the switching instructionsignal in question is inverted to effect changeover such that, regardingthe ON or OFF condition of the switching power device that supplies linecurrent relating to the signal whose level was the first to be invertedof two signals whose levels were the same, if the condition was ON, itbecomes OFF, while if OFF it becomes ON. Next, when the level of theremaining signal of the two signals whose levels were the same isinverted, the level of the switching instruction signal in question isinverted to change over the ON or OFF condition of the switching powerdevice that supplies the line current relating to the signal that waslikewise inverted.

At this time-point, the three signals: first, second and third switchinginstruction signals PU, PV and PW which are the outputs of the logiccircuit 10 have the same level which is coincident with the level of theone signal different from the level of the other two signals in thethree signals HU, HV and HW, at the timing of the rising edge of thestate update timing signal CLK10. These signals PU, PV and PW maintainthe last resultant level until the next timing of the rising edge of thestate update timing signal CLK10. Thus, the same operation is repeatedafter the timing of the subsequent rising edge of the state updatetiming signal CLK10.

Next, the operation will be described in the case where the levels ofthe three signals HU, HV and HW at the timing of the rising edge of thestate update timing signal CLK10 are all the same.

In the case where the levels of the three signals HU, HV and HW are allthe same, the signal levels of PU, PV and PW that were fixed at thetiming of the rising edge of the state update timing signal CLK10 aremaintained until the timing of the next rising edge of the state updatetiming signal CLK10.

The construction of the logic circuit 10 of the first embodiment of thepresent invention is described in more detail below.

The internal construction of the logic circuit 10 is described withreference to FIG. 4, explaining the operation of the structuralelements. In FIG. 4, reference numerals 36, 37, 38, 39, 40 and 41 arefirst, second, third, fourth, fifth and sixth data selectors, havingtheir operation such that when an input terminal SEL is H level, thelevel of an input terminal B is output at an output terminal Y and whenthe input terminal SEL is L level, the level of an input terminal A isoutput at the output terminal Y. In this construction, the first tothird data selectors 36 to 38 are included in a first data selectingsection 20, while the fourth to sixth data selectors 39 to 41 areincluded in a second data selecting section 21.

Next, reference numerals 26, 27, and 28 are first, second and thirdreset-priority RS flip-flops, and when an input terminal R for reset isH level and an input terminal S for set is L level, the signal level ofthe RS flip-flops is reset and the signal level of an output terminal Qis changed to L level. In the meanwhile, when an input terminal R is Llevel and input terminal S is H level, the signal level of the RS flipflops is set and the signal level of the output terminal Q is changed toH level. When the input terminal R is H level and input terminal S isalso H level, the signal level of each RS flip-flop is reset, resetbeing prioritized, and the signal level of the output terminal Q ischanged to L level.

Next, reference numerals 29, 30, 31, 12, 13, and 14 are first, second,third, fourth, fifth and sixth D-latches, where the first to thirdD-latches 29 to 31 are included in the second data latch section 15,while the fourth to sixth D-latches 12 to 14 are included in the firstdata latch section 34, and where each of the D-latches has three inputterminals D, CK and PR and one output terminal Q. In this construction,the signal level of the D input terminal is latched at the timing of therising edge of the clock pulse signal CLK1 or CLK10 input to the inputterminal CK and then generates an output signal of this latched levelthrough the output terminal Q. Each input terminal PR is for inputting apreset signal, and if H level is input, namely, when the RESET signalbecomes active in the broader stair including the D-latch, the presetsignal for the D-latch becomes active so that the D-latch is preset withmaximum priority and H level is output through the output terminal Q.

Next, 23, 24, 25, 127, 128, 129, 130, 131 and 132 are first, second,third, fourth, fifth, sixth, seventh, eighth, and ninth inverting gates,and if H level is input at their input terminals, L level is output attheir output terminals, and if L level is input at their inputterminals, H level is output at their output terminals. Referencenumeral 22 is a data decoder unit, having input terminals A, B and C andoutput terminal Y, and its truth table is shown in Table 1.

It should be noted that the truth table (Table 1) can easily beimplemented by AND, OR and inverting gates.

                  TABLE 1                                                         ______________________________________                                        INPUT     OUTPUT                                                              ______________________________________                                        A    B     C      Y = A · B · C + A · B                              · C + A · B · C + A                                · B · C                                   L    L     L       L                                                          L    L     H       H                                                          L    H     L       H                                                          L    H     H       L                                                          H    L     L       H                                                          H    L     H       L                                                          H    H     L       L                                                          H    H     H       H                                                          ______________________________________                                    

Reference numeral 35 denotes a timing signal distributing unit whichreceives the system clock CLK1 and state update timing signal CLK10 andgenerates a state update timing delay signal CLK11. The relationship ofCLK1, CLK10 and CLK11 will now be described with reference to FIG. 5.First of all, it is to be assumed that the period of the state updatetiming signal CLK10 is considerably larger than the period of the systemclock CLK1 and that the update timing signal CLK10 is changed insynchronization with the timing of the trailing edge (e.g., at time 1)of the system clock CLK1. Next, the state update timing delay signalCLK11 is assumed to be a signal obtained by delaying the state updatetiming signal CLK10 by an amount of half the time interval between thetrailing edge and the rising edge (e.g., at time 3) of the system clockCLK1.

In more detail, the operation of the logic circuit 10 is now describedbelow.

The input terminals A of the first, second, and third data selectors 36,37 and 38 will be respectively referred to as input terminals 1A, 2A and3A of the first data selecting section 20 while their input terminals Bwill be respectively referred to as input terminals 1B, 2B and 3B of thefirst data selecting section 20, while the input terminals SEL beingconnected in common to constitute the input terminal SEL of the firstdata selecting section 20.

Also, the input terminals A of the fourth, fifth and sixth dataselectors 39, 40, and 41 will be referred to collectively as inputterminals 1A, 2A and 3A of the second data selecting section 21 whiletheir input terminals B will be respectively referred to as inputterminals 1B, 2B and 3B of the second data selecting section 21, withinput terminals SEL being connected in common to constitute the inputterminal SEL of the second data selecting section 21.

Also, the input terminals D of the first, second, and third D latcheswill be referred to respectively as input terminals 1D, 2D and 3D offirst data latch section 34, with the input terminals CK being connectedin common to constitute input terminal CK of first means 34 for datalatching, input terminals PR being connected in common to constituteinput terminal PR of the first data latch section 34, with the outputterminals Q being respectively referred to as output terminals 1Q, 2Qand 3Q of first data latch section 34. The input terminals D of thefourth, fifth and sixth D latches 29, 30 and 31 will be referred torespectively as input terminals 1D, 2D and 3D of the second data latchsection 15, with the input terminals CK being connected in common toconstitute input terminal CK of second data latch section 15, with theinput terminals PR being connected in common to constitute inputterminal PR of the second data latch section 15, with the outputterminals Q being respectively referred to as output terminals 1Q, 2Qand 3Q of the second data latch section 15.

Also the outputs of the first data selecting section 20 will be referredto as first selection output signals Y1U, YIV, YIW and the outputs ofthe second data selecting section 21 will be referred to as secondselection output signals Y2U, Y2V, Y2W.

First of all, the first, second and third line current comparisonresults HU, HV and HW are input to the input terminals 1D, 2D, 3D of thefirst data latch section 34. At the same time, the first, second andthird line current comparison results HU, HV and HW are input to theinput terminals 1B, 2B, 3B of the first data selecting section 20 andare also input to the input terminals 1A, 2A, 3A thereof through thefirst, second and third inverting gates 23, 24, and 25, respectively.

The condition immediately after the state update timing signal CLK10changes from L level to H level i.e. when the rising edge thereof isinput, in other words, TIME 1 in FIG. 5 will be described.

First of all, the input levels of the input terminals 1D, 2D, and 3D ofthe first data latch section 34 are latched to be held and are outputthrough the output terminals 1Q, 2Q, and 3Q. This condition of the firstdata latch section 34 is maintained until the next rising edge of thestate update timing signal CLK10 is input. Next, the signals output fromthe output terminals 1Q, 2Q, and 3Q of the first data latch section 34are input to the data decoder unit 22 and the output terminal Y of thedata decoder unit 22 is made H level or L level in accordance with thetruth table of Table 1. Hereinbelow, the signal output from this outputterminal Y will be referred to as mode signal YM.

In this construction, the mode signal YM is input to the input terminalSEL of the first data selecting section 20 to generate the firstselection output signals YIU, YIV, Y1W in accordance with the modesignal YM.

Next, the condition immediately after the state update timing delaysignal CLK 11 changes from L level to H level i.e. a rising edge isinput; at TIME 2 in FIG. 5 will now be described.

First of all, the state update timing delay signal CLKll is input to therespective input terminals S of the first, second and third RSflip-flops 26, 27 and 28 and these flip-flops are set when the signalCLK11 is H level. However, as described earlier, the first, second andthird RS flip-flops 26, 27 and 28 are reset-priority RS flip-flops, soif the input terminal R is H level, reset is prioritized. The result isthat, in the first, second and third RS flip-flops 26, 27 and 28, onlythe flip-flop whose input terminal R is L level is set when the stateupdate timing delay signal CLK11 is H level.

The output signals of the first, second and third RS flip-flops 26, 27and 28 are input to the input terminals 1A, 2A, 3A of the second dataselecting section 21 and are also input to the input terminals 1B, 2B,3B thereof through the fourth, fifth and sixth inverting gates 127, 128,and 129, respectively. The mode signal YM generated by the data decoderunit 22 is input to the input terminal SEL of the second data selectingsection which outputs second selection output signals Y2U, Y2V, Y2W inaccordance with the mode signal YM.

Next, the following describes the condition immediately after the systemclock CLK1 changes from L level to H level, i.e., a rising edge thereofis input to the logic circuit 10 from the timing signal generator 11 atTIME 3 shown in FIG. 5.

First of all, when the rising edge of the system clock CLK1 is input tothe input terminal CK of the second data latch section 15, the seconddata latch section 15 latches the second selection output signals Y2U,Y2V, Y2W input through the input terminals 1D, 2D, and 3D, and outputsthe input latched signals through the output terminals 1Q, 2Q, and 3Q ofthe second data latch section 15, and these output signals are helduntil the timing of the next rising edge of the state update timingsignal CLK10. The output signals from 50 the output terminals 1Q, 2Q, 3Qof the second data latch section 15 are respectively fed to the seventh,eighth and ninth inverting gates 130, 131 and 132 to generate the first,second and third switching instruction signals PU, PV and PW serving asthe output signals of the current controller 6.

Since the first, second and third switching instruction signals PU, PVand PW are updated at the timing of inputting the rising edge of systemclock CLK1 to the input terminal CK of the second data latch section 15,these switching instruction signals are not changed at TIME 1 or TIME 2in FIG. 5.

The above description is of the operations from the time-point (TIME1)at which the state update timing signal CLK10 changes from L level to Hlevel to the time-point (TIME2) at which the state update timing delaysignal CLK11 changes from L level to H level and to the time-point(TIME3) at which the subsequent system clock CLK1 changes from L levelto H level. These operations are of the transition to the eight states:State No. A00, B00, C00, D00, E00, F00, G00, H00 in FIG. 3, which arethe operations at the timing of the rise (i.e., input of the risingedge) of the state update timing signal CLK10.

Next, the subsequent operation i.e. operation up to the time point ofthe next rising edge of the state update timing signal CLK10 is inputwill be described.

First of all, the following describes the case where a transition takesplace to any one of State No. A00, B00, C00, D00, E00, F00 in FIG. 3, inother words, the case where there are two signals of the same signallevel of the first, second and third line current comparison results HU,HV and HW at the timing of the rising edge of the state update timingsignal CLK10. The description will be herein given taking as an exampleof the state A00 of FIG. 3.

In the condition of State No. A00, the line current comparison result HUis L level, HV is H level, HW is H level as shown in FIG. 3, and themode signal YM is L level, the outputs of first means 20 for dataselection: Y1U is H level, Y1V is L level, Y1W is L level, the first RSflip-flop 26 is in the reset condition, second RS flip-flop 27 is in theset condition, and third RS flip-flop 28 is in the set condition. Also,the outputs of the second data selecting section 21: Y2U is L level, Y2Vis H level, and Y2W is H level.

The following describes the operation when the second line currentcomparison result HV changes from H to L level, i.e., the operation whena transition takes place from State No. A00 to State NO. AX1.

When the second line current comparison result HV changes from H to Llevel, the level of the first selection output signal Y1V is changedover from L level to H level and thereby second RS flip-flop 27 isreset, which causes the second selection output signal Y2V to be changedover from H to L level. Consequently, PU, PV and PW become (PU, PV,PW)=(H, H, L) at the timing of inputting the next rising edge of thesystem clock CLK1. In the next-stage, the main circuit power controlsection 8 operates in accordance with these first, second and thirdswitching instruction signals PU, PV and PW output from the currentcontroller 6.

Thereafter, the following describes the operation when the third linecurrent comparison result HW changes from H to L level i.e. theoperation in which a transition takes place from State No. AX1 to StateNo. AX2 in FIG. 3.

When the third line current comparison result HW changes from H to Llevel, the level of the first selection output signal Y1W is changedover from L level to H level and then the third RS flip-flop 28 isthereby reset, causing the second selection output signal Y2W to changeover from H level to L level.

PU, PV and PW therefore become (PU, PV, PW)=(H, H, H) at the timing ofinputting the next rising edge of the system clock CLK1. The next-stagepower control section 8 is operated in accordance with the first, secondand third switching instruction signals PU, PV and PW.

This condition i.e. (PU, PV, PW)=(H, H, H) is maintained until thetiming of the rising edge of the system clock CLK1 after the timing ofthe next rising edge of the state update timing signal CLK10.

The foregoing was a description of the operation in the case where atransition took place to one of State No. A00, B00, C00, D00, E00, F00at the timing of the rising edge of the state update timing signal CLK10i.e. the case where there were two signals with the same signal level ofthe first, second and third line current comparison results HU, HV andHW at the timing of the rising edge of the state update timing signalCLK10. However, the case will now be described where a transition nexttakes place to any one of State No. G00, H00 in FIG. 3, i.e. the casewhere all of the first, second and third line current comparison resultsHU, HV and HW at the timing of the rising edge of state update timingsignal CLK10 have the same signal level.

The following describes an operation taking as an example of thecondition of State No. G00 in FIG. 3. In the condition of State No. G00,the line current comparison result HU is H level, HV is H level, HW is Hlevel, mode signal YM is H level, the output of the first data selectingsection 20 Y1U is H level, Y1V is H level, Y1W is H level, and thefirst, second and third RS flip-flops 26, 27 and 28 are all in the resetcondition.

As a result, the output of the second data selecting section 21: Y2U isH level, Y2V is H level, Y2W is H level, so, regarding PU, PV and PW, atthe timing of the next rising edge of the system clock CLKl, PU becomesL level, PV becomes L level and PW becomes L level, and thus thenext-stage power control section 8 is operated in accordance with theresultant PU, PV and PW.

This condition (PU, PV, PW)=(L, L, L) is maintained until the timing ofthe rising edge of the system clock CLK1 after the timing of the nextrising edge of the state update timing signal CLK10.

The above is a description of the operation in the transition from StateNo. A00 to State No. AX1 and then to State No. AX2 and of the transitionto State No. G00 at the timing of the rising edge of the state updatetiming signal CLK10. In this connection, the other state transitions inFIG. 3 can be inferred in the same way from the above description, soexplanation thereof is omitted.

The following describes an operation and way of controlling the linecurrents of the three-phase AC power source 1 in the case where the linecurrent instructions are sine wave signals with reference to FIGS. 6A to6C.

FIG. 6A shows the first, second and third line current instructions iTU,iTV, and iTW and the first, second and third line current measurementresults iFU, iFV, and iFW; FIG. 6B shows the action of the logic circuit10 regarding a dotted line portion of FIG. 6A shown to a larger scale;and FIG. 6C shows the ON/OFF action of the first, second, third, fourth,fifth and sixth switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 inresponse to the output levels of the first, second and third switchinginstruction signals PU, PV and PW generated by the logic circuit 10.

First of all, the operation of the PWM converter at time-point t=t1 i.e.at the timing of the rising edge of the state update timing signal CLK10will be described.

At time t=t1, the magnitude relationships of iTU, iTV, iTW and iFU, iFV,iFW at the timing of the rising edge of state update timing signal CLK10are as below:

iTU>iFU

iTV<iFV

iTW<iFW and

the first, second and third line current comparison results HU, HV andHW are (HU, HV, HW)=(L, H, H).

This condition corresponds to State No. A00 in the truth table of FIG. 3and the switching instruction signals PU, PV and PW output from thelogic circuit 10 become (PU, PV, PW)=(H, L, L) and these signals aretransmitted to the main circuit control section 8. Thus, the switchingpower devices Q1, Q2, Q3, Q4, Q5 and Q6 are respectively turned OFF, ON,ON, ON, OFF, OFF and line current measurement results iFU, iFV, and iFWapproach the line current instructions iTU, iTV, and iTW in accordancewith the electric time constant of the three-phase AC power source 1.

Next, the operation will be described when iTV>iFV, at the timing(t=t11) of changing the condition of the line current comparison resultsfrom (HU, HV, HW)=(L, H, H) to (HU, HV, HW)=(*, L, H).

Since the level of HU is ignored, so, for convenience in description,HU=* is taken to mean DON'T CARE. Hereinbelow `*` is taken to mean DON'TCARE. The logic circuit 10 receives the first, second and third linecurrent comparison results HU, HV and HW, and changes over the outputfirst, second and third switching instruction signals PU, PV and PW fromthe condition (PU, PV, PW)=(H, L, L) to the condition (PU, PV, PW)=(H,H, L), changes the switching power device Q2 to OFF and Q5 to ON, whichcorresponds to the transition from State No. A00 to State No. AX1).

Next, the operation will be described when iTW>iFW, at the timing(t=t12) of changing the condition of the line current comparison resultsfrom (HU, HV, HW)=(*, L, H) to (HU, HV, HW)=(*, L, L).

The logic circuit 10 receives the first, second and third line currentcomparison results HU, HV and HW, and changes over the signal levelconditions of the first, second and third switching instruction signalsPU, PV and PW from (PU, PV, PW)=(H, H, L) to (PU, PV, PW)=(H, H, H), andthen changes the switching power device Q3 to OFF and Q6 to ON, whichcorresponds to the transition from State No. AX1 to State No. AX2.

The condition of (PU, PV, PW)=(H, H, H) obtained at time-point t=t12isthen maintained until the timing of the next rising edge of the stateupdate timing signal CLK10.

Likewise, by performing the same operation after the next timing of therising edge of the state update timing signal CLK10, the line currentsof the three-phase AC power source 1 are controlled such as to conformto the first, second and third line current instructions iTU, iTV, andiTW.

It should be noted that, in FIG. 1, in the base drive circuit 4 forcontrolling the main circuit switching power devices Q1, Q2, Q3, Q4, Q5and Q6 in accordance with the output levels of PU, PV and PW output fromthe current controller 6, a construction may be employed such that thereis a fast change from ON to OFF and a fixed time delay is applied whenthe respective switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 changefrom OFF to ON. In this construction, for example, when changing from acondition in which Q1 is ON and Q4 is OFF to a condition in which Q1 isOFF and Q4 is ON, first of all Q1 is turned OFF and after Q1 hasdefinitely completed OFF, Q4 is turned ON. By this arrangement, it ispossible to avoid the risk that, at the timing where Q1 and Q4 changeover, they may be instantaneously simultaneously ON to cause a largecurrent to flow to the switching power devices.

Also, while in the comparators 17 to 19 in FIG. 2, the line currentinstruction is input to the inverting input terminal and the linecurrent measurement result is input to the non-inverting terminal,another construction of comparator means can be of course employed asshown in FIG. 7, where a line current instruction of inverse phase withrespect to the line current to be input is input to the comparatormeans.

Also, although, in FIG. 1, the power source current detector 9 isprovided between the three-phase AC power source 1 and the reactor 59,it could of course be provided between the reactor 59 and the maincircuit power control section 8.

Also, in cases such as where current cut off is performed as protectionon overload of the PWM converter, it would of course be possible to addin the base drive section 4 a function of making a condition that all ofQ1˜Q6 can be put into OFF condition for cutting off the current.

The same operation can of course be performed in power regeneration.

With the first embodiment of the present invention as described above,the construction has no current error amplifier provided, so theproblems involved in gain adjustment of a current error amplifier can beessentially solved and no gain adjustment at all is necessary.

Furthermore, even if there are changes in the characteristics andspecification of reactor 59, power source current detector 9, currentcontroller 6, or main circuit power control section 8, operation isalways such as to make the line current errors the minimum, and even inthe presence of manufacturing variation of performance and temperaturecharacteristics etc., operation is always such as to make the linecurrent errors the minimum, so current control response is excellent andthere is no risk of oscillation. Also, even if the value of the DCvoltage changes, there is no need to adjust the gain and operation isperformed such that the line current error is always minimum. Also,apart from first, second and third comparators, the current controller 6in a PWM converter according to the present invention can be constructedentirely of digital circuitry, and therefore the portion that isconstructed of simple digital circuitry has no risk of offset or driftand is of low cost, desirably.

Furthermore, as the first line current instruction, second line currentinstruction and third line current instruction respectively, byemploying an in-phase sine wave signal or inverse-phase sine wave signalwith respect to the respective phase voltages seen from the neutralpoint of the three-phase AC power source 1, reduction of the phasedifference between the phase voltages and line currents, in other words,improvement of the power factor, can be achieved, and since the controlcan be performed such that the line currents are sine waves, distortionof the line currents can be suppressed, in other words, higher harmonicsof the power source can be reduced.

Consequently, with the present invention, there can be provided a PWMconverter wherein the task of adjustment of the gain of the currenterror amplifiers and/or the task of offset adjustment are unnecessaryyet which has excellent current control response.

(Embodiment 2)

The following describes a second embodiment of a PWM converter accordingto the present invention with reference to FIGS. 8 and 9. In the secondembodiment, FIG. 8 shows a construction of a logic circuit 10 providedin the current controller 6, where the internal structure of the logiccircuit is different from that of the first embodiment shown in FIG. 4.The rest of the construction of the PWM converter of the secondembodiment is exactly the same as that of the first embodiment, so thedetailed description thereof is omitted here. Hereinbelow, thedescription will be concerned with the construction of the logic circuit10 and its operation in the second embodiment.

Before the description of the logic circuit 10 proceeds, it is notedthat, since the way of reading the truth table of the logic circuit 10shown in FIG. 9 is exactly the same as that of the first embodiment, sothe description thereof is omitted here.

Also, the operation of the logic circuit 10 based on the truth tableshown in FIG. 9 is generally the same as that of the logic circuit 10 ofthe first embodiment, so the description thereof is likewise omittedhere.

The logic circuit 10 reads the first, second and third line currentcomparison results HU, HV and HW at the timing of the rising edge of thestate update timing signal CLK10 and determines the signal levels of theswitching instruction signals PU, PV and PW in accordance with thecomparison results HU, HV and HW, which the operation in this regard isexactly the same as that of the logic circuit 10 described in the firstembodiment.

Next, regarding the operation of the logic circuit 10 up to the timingof the next rising edge of the state update timing signal CLK10, in asimilar manner to the operation of the logic circuit 10 in the firstembodiment, the operation is described in the two cases, i.e, in thefirst case where one of the signal levels of the three signals HU, HV,HW is different from the level of the other two signals, namely:##EQU3## and in the second case where all three signals are in the samelevel, namely: ##EQU4##

First, the following describes the operation in the case where the levelof one signal is different from the other two signals of the threesignals HU, HV and HW at the timing of the rising edge of the stateupdate timing signal CLK10.

First, the level of the switching instruction signal in question isinverted to effect changeover such that if the ON or OFF condition of aswitching power device that supplies line current relating to the onesignal of the two signals having the same levels of which level was thefirst to be inverted was ON, it becomes OFF while if it was OFF, itbecomes ON. This is exactly the same as the operation of the logiccircuit 10 in the first embodiment. Subsequently, however, the operationdiffers from that of the first embodiment in that, when the level of theremaining signal of the two signals having the same levels is inverted,the ON/OFF of the switching power device that supplies line currentrelating to the signal having its level inverted is not changed over butinstead the level of the other two switching instruction signals isagain inverted.

At this time-point, the three signals PU, PV, and PW of the switchinginstruction signals constituting the output of the logic circuit 10 havethe same level, but these three signals PU, PV, and PW maintain theirlevel until the timing of the next rising edge of the state updatetiming signal CLK10, where these three signals PU, PV, and PW havelevels which are the inverse of that of the one signal of which thelevel was different at the timing of the rising edge of the state updatetiming signal CLK10. The relationship of the signal levels is mutuallyinverted from those of the first embodiment. The same operation isrepeated after the timing of the next rising edge of the state updatetiming signal CLK10.

Next, in the case where the levels of the three signals HU, HV and HWare all the same at the timing of the rising edge of the state updatetiming signal CLK10, the operation is the same as that of the firstembodiment and the description thereof is omitted here.

The construction of the logic circuit 10 provided in the currentcontroller 6 according to the second embodiment is described in moredetail below.

Regarding the internal construction of the logic circuit 10, parts whichare different from the first embodiment will be described with referenceto FIG. 8. First of all, the operation of the structural elements thatare newly provided with respect to the logic circuit 10 of the firstembodiment will be described below.

Reference numerals 135 and 136 denote first and second AND circuits andwhen H level signals are input to all of the input terminals of thethree input terminals of the first AND circuit 135, H level is output atthe output terminal. Also, when H level signals are input to all of thetwo input terminals of the second AND circuit 136, H level is output atthe output terminal. If at least one of the input terminals is L level,L level is output at the output terminal in the first and second ANDcircuits.

Besides these elements, there are newly provided a seventh selector 42,a seventh D latch 16, and tenth and eleventh inverting gates 133 and134. However, the operation of these structural elements is exactly thesame as in the first embodiment, so the description of their operationis omitted here.

In the arrangement of these structural elements, the output terminal Yof the data decoding unit 22 is connected through the tenth invertinggate 133 to an input terminal A and is directly connected to anotherinput terminal B of the seventh data selector 42. The output terminal Yof the seventh data selector 42 is connected to the input terminal SELof the second data selecting section 21 while the input terminal SEL ofthe seventh data selector 42 is connected to the output terminal Q ofthe seventh D latch 16. An input terminal D of the seventh D latch 16 isearthed to be always L level and another input terminal CK is connectedwith the output terminal of the first AND circuit 135 and further inputterminal PR of the seventh D latch 16 is connected to the outputterminal of the second AND circuit 136.

The output terminals Q of the first, second and third RS flip-flops 26,27 and 28 are respectively connected through the fourth, fifth and sixthinverting gates 127, 128, and 129 to the three input terminals of thefirst AND circuit 135. The state update timing delay signal CLK11 isinput to one of the two input terminals of the second AND circuit 136through the eleventh inverting gate 134, while the state update timingsignal CLK10 is input to the other input terminal of the second ANDcircuit 136.

By this arrangement, in the seventh data selector 42, when the seventh Dlatch 16 is pre-set with its output terminal Q being H level to be inputto the input terminal SEL of the seventh data selector 42, the signallevel input to the input terminal B is output at the output terminal Y.When the input terminal CK of the seventh D latch 16 is changed overfrom L level to H level, the output terminal Q becomes L level which isinput to the input terminal SEL of the seventh data selector 42,resulting in that the level input at input terminal A of the seventhdata selector 42 is output at the output terminal Y.

In this arrangement, the occasion for the presetting of the seventh Dlatch 16 is when the state update timing delay signal CLK11 is L leveland the state update timing signal CLK10 is H level. Meanwhile, theoccasion for the changeover of the input terminal CK from L level to Hlevel is when the first, second and third RS flip-flops 26, 27 and 28are all pre-set.

The operation of the logic circuit 10 constructed as above will now bedescribed.

In view of FIG. 5, in the duration prior to the rising edge of the stateupdate timing delay signal CLK11, since the state update timing signalCLK10 is H level and the state update timing delay signal CLK11 is Llevel, the seventh D latch 16 is pre-set, and therefore a signal of thesame level as that of the mode signal YM output from the data decodingunit 22 is input to the common input terminal SEL of the second dataselecting section 21.

In contrast, the level at the input terminal SEL of the second dataselecting section 21 cannot be inverted until all of the first, secondand third RS flip-flops 26, 27 and 28 are in the reset condition.

Consequently, when a transition takes place to any one of State Nos.A00, B00, C00, D00, E00, F00 shown in FIG. 9, i.e., in the case wherethere are two signals of the same signal level in the first, second andthird line current comparison results HU, HV and HW at the timing of therising edge of the state update timing signal CLK10, the operation oftransition from the levels of PU, PV and PW which were fixed at thetiming of the rising edge of the state update timing signal CLK10 up tothe transition of the operation where any one of the three signals PU,PV and PW is first inverted in level is exactly the same as in the firstembodiment. Subsequently, when the remaining one of HU, HV, HW isinverted, all the first, second and third RS flip-flops 26, 27 and 28are reset, so that the level of the input terminal SEL of the seconddata selecting section 21 is inverted as shown by State No. AX2, AY2,BX2, BY2 etc. of FIG. 9, which the levels are the inverse of those shownin FIG. 3 in the first embodiment.

The levels resulting from the changeover is maintained until the timingof the rising edge of the system clock CLK1 subsequent to the timing ofthe rising edge of the next state update timing signal CLK10, which theoperation is the same as in the first embodiment.

Next, the following describes the case where a transition takes place toany one of State Nos. G00, H00 in FIG. 9, i.e., the case where all ofthe first, second and third line current comparison results HU, HV andHW at the timing of the rising edge of the state update timing signalCLK10 were the same level.

In view of FIG. 5, at the timing of the rising edge of the state updatetiming signal CLK10, the first, second and third RS flip-flops 26, 27and 28 are all reset. In this duration, the seventh D latch 16 is in thepre-set condition up to the timing of the rising edge of the stateupdate timing delay signal CLK1, and the level of the input terminal SELof the second data selecting section 21 is unchanged, so the operationin this case is exactly the same as the operation of the firstembodiment, as shown in FIG. 9.

As described above, in the operation of the logic circuit 10 accordingto the second embodiment of the present invention, when comparing thefirst embodiment of FIG. 3 and the second embodiment of FIG. 9, the onlydifference is that, in this second embodiment, only when the level ofone signal of the three signals HU, HV and HW, is different at thetiming of the rising edge of the state update timing signal CLK10, thesignal levels of PU, PV and PW whose levels are mutually equal as theresult of the final transition of the operation, are the inverse of thelevels of PU, PV and PW in the first embodiment.

Regarding the levels of PU, PV and PW, when the switching instructionsignals PU, PV and PW are mutually the same, the inter-line voltages ofthe respective lines of the three-phase AC power source 1 become zero.Therefore, whether PU, PV, PW are H, H, H or L, L, L in level, there isno change in the inter-line voltages of the respective lines up to thetiming of the next rising edge of the state update timing signal CLK10.In the second embodiment, therefore, the line currents of thethree-phase AC power source 1 can be controlled in exactly equivalentfashion to the first embodiment. It should be noted that a modifiedarrangement of FIG. 9 would be possible where PU, PV and PW at State No.G00 are H, H, H and PU, PV and PW at State No. H00 are L, L, L.

(Embodiment 3)

In the third embodiment of the present invention, as shown in FIG. 10,the internal structure of the current controller 6 provided in the PWMconverter is different from that of the first embodiment or the secondembodiment shown in FIG. 2. The remaining of the third embodiment of thepresent invention is the same as the first embodiment or secondembodiment except for the fact that, as the structural elements of thecurrent controller 6 as shown in FIG. 10, there are newly providedfirst, second and third double-reading logic circuits 48, 49 and 50interconnected between the comparators 17 to 19 and the logic circuit10.

The first, second and third double-reading logic circuits 48, 49, and 50respectively have exactly the same construction, so the construction andoperation of the first double-reading logic circuit 48 will be describedbelow using a typical double-reading logic circuit shown in FIG. 11.

In FIG. 11, reference numerals 51, 52 and 69 denote eighth, ninth andtenth D-latches each having three input terminals PR, D and CK and anoutput terminal Q. In this construction, the level of the input terminalD is latched at the timing of the rising edge of the signal input to theinput terminal CK receiving a system clock pulse CLK2 and the latchedlevel at the input terminal D is output through the output terminal Q.The input terminal PR is for receiving a pre-set signal, and when Hlevel is input to the input terminal PR, the D latch is preset withpriority and the signal level at the output terminal Q becomes H level.Also, the input terminals CK of the eighth, ninth and tenth D latches51, 52 and 69 are connected in common while the input terminals PR ofthe eight, ninth and tenth D latches 51, 52, and 69 are connected incommon receiving RESET signal for preset.

Reference numerals 137, 138 and 70 denote twelfth, thirteenth, andfourteenth inverting gates, and when H level is input at their inputterminals, they output L level at their output terminals and vice versa.Reference numeral 53 denotes a fourth RS flip-flop, and when the inputterminal R is H level and input terminal S is L level, it is reset tochange the condition of the output terminal Q to L level, and when theinput terminal R is L level and input terminal S is H level, it is setto change the condition of the output terminal Q to H level. Referencenumerals 54 and 55 denote third and fourth AND circuits, and when alltheir input terminals are fed with H level signals, they output H leveloutput signal, and for otherwise inputs, they output L level outputsignal.

The following describes the operation of the first double-reading logiccircuit 48 in more detail with reference to the signal flow.

In the first stage, the level of the first line current comparisonresult HU input to the input terminal SI of the first double-readinglogic circuit 48 is latched and held in the eighth D latch 51 at thetiming of the rising edge of the system clock CLK2 and the latched levelis output at the output terminal Q.

At the timing of the next rising edge of the system clock CLK2, thelevel of the output terminal Q of the eighth D latch 51 is latched andheld in the ninth D latch 52 and is output at its output terminal Qwhile the level of the comparison result HU at this time is latched andheld in the eighth D latch 51 and is output at its output terminal Q.

The output levels of the output terminals Q of the eighth and ninth Dlatches 51 and 52 are respectively fed to fourth AND circuit 55 and arealso transmitted through the twelfth and thirteenth inverting gates 137,138 to the third AND circuit 54. Then the output of the third ANDcircuit 54 is fed to the input terminal R of the fourth RS flip-flop 53and the output of the fourth AND circuit 55 is fed to the input terminalS of the fourth RS flip-flop 53. The level of the output terminal Q ofthe fourth RS flip-flop 53 is then latched by the tenth D latch 69 atthe timing of the trailing edge of the system clock CLK2.

In this construction, the system clock CLK2 is logically inverted bymeans of the fourteenth inverting gate 70 and the resultant invertedsignal is fed to the input terminal CK of the tenth D latch 69.Therefore, the input signal level at the input terminal D of the tenth Dlatch 69 is latched at the timing of the trailing edge of the systemclock CLK2. The output terminal Q of the tenth D latch 69 then generatesa signal HU1 as the output signal of the first double-reading logiccircuit 48.

From the above operation, it can be seen that the first double-readinglogic circuit 48 performs an operation of checking the input signal HUat every timing of the rising edge of CLK2, and if the checking resultcontinues to be H level twice, the output signal HU1 is altered to Hlevel, and if the checking result continues to be L level twice, theoutput signal HU1 is altered to L level.

The above is a description of the internal operation of the firstdouble-reading logic circuit 48 and this is exactly the same for thesecond and third double-reading logic circuits 49 and 50.

The first, second and third double-reading logic circuits 48, 49, and 50therefore make it possible to generate the output signals HU1, HV1, HW1from which signal fluctuation due to very short-period noise containedin the signals HU, HV, HW, i.e., H level→L level→H level or L level→Hlevel→L level, has been removed.

It should be noted that, in FIG. 11, by providing three or more Dlatches and taking the AND of the output levels of the D latches, itwould be possible to set the number of times of reading the timing ofthe rising edge of the system clock CLK2 to three or more.

With the third embodiment of the present invention as described above,by adopting a construction where the first, second and thirddouble-reading logic circuits 48, 49, and 50 are provided and respectiveoutput signals HU, HV, HW of the first, second and third comparatorunits 17, 18 and 19 in the current controller are transmitted to thelogic circuit 10 through the first, second and third double-readinglogic circuits 48, 49, and 50 respectively, the noise superimposed onthe output signals of the first, second and third comparator units 17,18 and 19 can be removed. Thus, the line currents of three-phase ACpower source 1 can be controlled to coincide accurately with the first,second and third line current instructions iTU, iTV, and iTW even underconditions where noise is likely to be generated.

It should be noted that the same benefit will of course be obtainedwhether the first, second and third double-reading logic circuits 48,49, and 50 of the present embodiment are added to the first embodimentor the second embodiment.

(Embodiment 4)

FIG. 12 shows an internal construction of a logic circuit 10 provided ina current controller 6 of the PWM converter according to a fourthembodiment of the present invention.

Comparing the internal construction of the logic circuit 10 shown inFIG. 12 of the fourth embodiment with that of the first embodiment shownin FIG. 4, the constructions are generally the same except for the factthat, a construction is adopted where the output signals PU1, PV1, PW1of the seventh, eighth and ninth inverting gates 130, 131 and 132 areinput to first, second and third delay units 56, 57 and 58 for delayingswitching instruction signals, which the output signals are transmittedto the main circuit power control section 8 as the first, second andthird switching instruction signals PU, PV and PW.

The following describes the operation of the first, second and thirddelay units 56, 57 and 58 for delaying the switching instructionsignals.

The first, second and third delay units 56, 57 and 58 for delaying theswitching instruction signals are so constructed as to respectivelyreceive the output signals PU1, PV1, PW1 output from the seventh, eighthand ninth inverting gates 130, 131 and 132 and delay these signals PU1,PV1, PW1 by predetermined times in accordance with a predetermined ruleand then transmit the delayed signals to the main circuit power controlsection 8 as the first, second and third switching instruction signalsPU, PV and PW. Specifically, the construction is such that, in FIG. 3and FIG. 9, the delay time is 0 only when shifting to State Nos. A00,B00, C00, D00, E00, F00, C00, H00, but when shifting to other states,the first, second and third switching instruction signals PU, PV and PWdelayed by a predetermined time are output from the delay units 56, 57and 58.

The following describes the operation of a current-control type PWMconverter according to the fourth embodiment controlling the linecurrents of a three-phase AC power source 1 with reference to FIG. 3 andFIGS. 13A-13C.

FIG. 13A shows the first, second and third line current instructionsiTU, iTV, and iTW and first, second and third line current measurementresults iFU, iFV, and iFW. FIG. 13B shows the action of the logiccircuit 10 provided with the first, second and third delay units 56, 57and 58 for delaying the switching instruction signals in connection withthe dotted-line section of FIG. 13A to a larger scale. FIG. 13C showsthe ON/OFF operation of the switching power devices Q1, Q2, Q3, Q4, Q5and Q6 based on the output levels of the first, second and thirdswitching instruction signals PU, PV and PW, which are the outputs ofthe first, second and third delay units 56, 57 and 58.

First of all, the operation at time-point t=t1 i.e. at the timing of therising edge of the state update timing signal CLK10 will be described.

At time-point t=t1, where the magnitude relationship of iTU, iTV, iTWand iFU, iFV, iFW at the timing of the rising edge of the state updatetiming signal CLK10 is:

iTU>iFU

iTV<iFV

iTW<iFW

the first, second and third line current comparison results HU, HV andHW are (HU, HV, HW)=(L, H, H).

This condition corresponds to State No. A00 in the truth table of FIG. 3as represented by (HU, HV, HW)=(L, H, H), and therefore the levels ofPU1, PV1, PW1 become (PU1, PV1, PW1)=(H, L, L).

At this point, the first, second and third delay units 56, 57 and 58generate the changes of the signal level of PU1, PV1, PW1 as the outputPU, PV, PW which are supplied to the main circuit power control section8.

Accordingly, the switching power devices Q1, Q2, Q3, Q4, Q5 and Q6 arerespectively turned OFF, ON, ON, ON, OFF, OFF, and then the first,second and third line current measurement results iFU, iFV, and iFWapproach nearly equal to the first, second and third line currentinstructions iTU, iTV, and iTW in accordance with the electrical timeconstant of the three-phase AC power source 1. The above is adescription of the operation of transition to State No. A00 at thetiming of the rising edge of the state update timing signal CLK10 attime-point t=t1.

Next, the operation is described where the relationship becomes iTV>iFVat the timing when a change takes place from (HU, HV, HW)=(L, H, H) to(HU, HV, HW)=(*, L, H) at a time-point t=t11.

The logic circuit 10 receives these signals HU, HV, HW and changes overthe level condition of PU1, PV1, PW1 from (PU1, PV1, PW1)=(H, L, L) to(PU1, PV1, PW1)=(H, H, L). In this operation, at the time-point t=t111after the lapse of a pre-set delay time TD from the changeover of PV1from L level to H level, the second delay unit 57 changes over from (PU,PV, PW)=(H, L, L) to (PU, PV, PW)=(H, H, L) so that the switching powerdevice Q2 is changed over to OFF while the switching power device Q5 ischanged over to ON.

By this operation, a drop of the second line current measurement resultiFV is effected after a fixed time has passed relative to the secondline current instruction iTV (shift to State No. AX1).

Next, the operation is described where the relationship becomes iTW>iFWat the time-point t=t12 when a change takes place from (HU, HV, HW)=(*,L, H) to (HU, HV, HW)=(*, L, L).

The logic circuit 10 receives these signals HU, HV, HW and changes overthe level condition of PU1, PV1, PW1 from (PU1, PV1, PW1)=(H, H, L) to(PU1, PV1, PW1)=(H, H, H) . In this operation, at the time-point t=t112after the lapse of a pre-set delay time TD from the changeover of PW1from L level to H level, the third delay unit 58 changes over the outputsignal condition from (PU, PV, PW)=(H, H, L) to (PU, PV, PW)=(H, H, H)and then the switching power device Q3 is changed over to OFF while theswitching power device Q6 is changed over to ON.

By this operation, a drop of the third line current measurement resultiFW is suppressed after a fixed time has passed relative to the secondline current instruction iTW, which represents the shift to State No.AX2.

The above is a description of the operation at time-point t=t12. Thecondition (PU, PV, PW)=(H, H, H) is maintained until the timing of thenext rising edge of the state update timing signal CLK10.

By repeating the subsequent same operations after the timing of the nextrising edge of the state update timing signal CLK10, the line currentsof the three-phase AC power source 1 are controlled so as to follow thefirst, second and third line current instructions iTU, iTV, and iTW.

The above is a description of how the line currents of three-phase ACpower source 1 are controlled with the current-control PWM invertor ofthe fourth embodiment of the present invention.

As above, with the fourth embodiment of the present invention, aconstruction is adopted such that the logic circuit is provided with thefirst, second and third delay units for delaying a switching signal andthe output from the seventh, eighth and ninth inverting gates istransmitted to the main circuit power control section through the first,second and third delay units. By this arrangement, in the first, secondand third delay units, the delay time is made 0 only when shifting toState No. A00, B00, C00, D00, E00, F00, G00, H00 in FIG. 3 and FIG. 9,otherwise when shifting to other states, the first, second and thirdswitching instruction signals PU, PV and PW are transmitted to the maincircuit power control section 8 with a predetermined time delay.

By this arrangement, the line currents of the three-phase AC powersource 1 can be made to coincide very closely with the line currentinstructions.

It should be noted that although the present embodiment is made byadding the first, second and third delay units 56, 57 and 58 fordelaying switching instruction signals to the first embodiment, the samebenefit could of course be obtained by adding the first, second andthird delay units 56, 57 and 58 to the second embodiment.

As is clear from the above embodiments, according to the first aspect ofthe present invention, current error amplifiers are omitted, so that theproblems associated with gain adjustment of current error amplifiers areessentially solved and no gain adjustment at all is required.

Furthermore, operation is such that even if the characteristics andspecification of the reactors, power source current detector, currentcontroller or main circuit power control section change, the linecurrent errors are always kept to the minimum and operation is also suchthat even if there is manufacturing variation of the characteristics ortemperature characteristics etc. the line current errors are always keptto the minimum, and therefore excellent current control response can beprovided and there is no risk of oscillation.

Also, even if the DC voltage changes, there is no need to adjust thegain and operation is always performed to keep the line current errorsto be minimum.

Also, apart from the first, second and third comparators, the currentcontroller in a PWM converter according to the present invention can beconstructed entirely of simple digital circuitry, and the portionconstructed of digital circuitry has no risk of offset or drift and isof low cost.

The present invention can therefore provide a PWM converter in which anoperation to adjust the gain of the current error amplifiers and/or anoperation to adjust the offset are unnecessary, which has excellentcurrent control response, and which is of low cost.

As described above, according to the fourth aspect of the presentinvention, noise superimposed on the output signals of the first, secondand third comparison means can be removed and spurious operation due tonoise can be prevented even under conditions that are subject to noisegeneration and the line currents of the three-phase AC power source canbe controlled to coincide accurately with the first, second and thirdline current instructions.

Also, if, as set out in the fifth aspect of the invention, the logiccircuit has a construction such that the switching instruction signal ofwhether the first, second, third, fourth, fifth or sixth switching powerdevice respectively is turned to the ON condition or OFF condition isdetermined at the state update timing and the timing at which the first,second and third line current comparison results change and thatcomprises delay means so that output switching instruction signals ofthe first, second, third, fourth, fifth and sixth main circuit switchingpower devices are delayed by a predetermined time at the timing ofchanging the first, second and third line current comparison results,the line currents of the three-phase AC power source can be made tocoincide very closely with the line current instructions.

Also, as set forth in the sixth aspect of the present invention, thecurrent instruction generator has a construction that outputs a firstline current instruction, a second line current instruction and a thirdline current instruction consisting respectively of a sine wave that isin-phase or a sine wave that is in anti-phase with respect to each phasevoltage, seen from the neutral point of the three-phase ac power source,a reduction in phase difference between the phase voltages and the linecurrents i.e. improvement in the power factor can be achieved and sinceeach line current can be controlled to a sine wave, distortion of theline currents can be suppressed i.e. higher harmonics of the powersource can be reduced.

What is claimed is:
 1. A PWM converter in a three phase bridgeconfiguration comprising:a power source current detector (9) fordetecting first, second and third line currents (IU, IV, IW) of athree-phase AC power source (1) and generating first, second and thirdline current measurement results (iFU, iFV, iFW); a current instructinggenerator (7) for generating first, second and third line currentinstruction values (iTU, iTV, iTW); a main circuit controller (6) whichincludes first, second and third comparators (17, 18, 19) comparing thefirst, second and third line current measurement results with the first,second and third line current instruction values respectively to outputfirst, second and third line current comparison results (HU, HV, HW),and a logic circuit (10) generating first, second and third switchinginstruction signals (PU, PV, PW) based on the first, second and thirdline current comparison results to switch the switching power means(Q1-Q6) on and off in a manner such that the first, second and thirdline current measurement results coincide as closely with the first,second and third line current instruction values, respectively.
 2. ThePWM converter as claimed in claim 1, wherein said first, second andthird comparators (17, 18, 19) output the line current comparisonresults of a first level when the first, second and third line currentmeasurement results are larger than the first, second and third linecurrent instruction values, respectively, and output the line currentcomparison results of a second level when the first, second and thirdline current measurement results are smaller than the first, second andthird line current instruction values, respectively, and wherein saidswitching power means is comprised of first, second, third, fourth,fifth and sixth switching power devices (Q1, Q2, Q3, Q4, Q5, Q6), sothat the logic circuit determines the levels of the switchinginstruction signals for putting the first, second, third, fourth, fifthand sixth switching power devices in the on and off conditions,respectively.
 3. The PWM converter as claimed in claim 2, wherein saidlogic circuit is adapted to determine the switching instruction signalssuch that,at said state update timing, when the first line currentcomparison result (HU) is of a first level (iFU>iTU) and he second linecurrent comparison result (HV) is of a second level (iFV<iTV) and thethird line current comparison result (HW) is of a second level(iFW<iTW), the second, third and fourth switching power devices areswitched to the of condition while the first, fifth and sixth switchingpower devices are switched to the on condition, and then in thesubsequent period from the time-point where the second line currentcomparison result (HV) becomes of a first level up to a time-point ofthe next state update timing, the fifth switching power device isswitched to the off condition while the second switnching power deviceis switched to the on condition, and then in the subsequent period fromthe time-point where third line current comparison result (HW) becomesof a first level up to a time-point of the next state update timing, thesixth switching power device is switched to the off condition while thethird switching power device is switched to the on condition; and atsaid state update timing, when the first line current comparison result(HU) is of a second level (iFU<iTU) and the second line currentcomparison result (HV) is of a first level (iFV>iTV) and the third linecurrent comparison result (HW) is of a second level (iFW<iTW), thefirst, third and fifth switching power devices are switched to the offcondition while the second, fourth and sixth switching power devices areswitched to the on condition, and then in the subsequent period from thetime-point where the first line current comparison result (HU) becomesof a first level up to a time-point of the next state update timing, thefourth switching power device is switched to the off condition while thefirst switching power device is switched to the on condition, and thenin the subsequent period from the time-point where the third linecurrent comparison result (HW) becomes of a first level up to atime-point of the next state update timing, the sixth switching powerdevice is switched to the off condition while the third swithing powerdevice is switched to the on condition; and at said state update timing,when the first line current comparison result (HU) is of a second level(iFU<iTU) and the second line current comparison result (HV) is of asecond level (iFV<iTV) and the third line current comparison result (HW)is of a first level (iFW>iTW), the first, second and sixth switchingpower devices are switched to the off condition while the third, fourthand fifth switching power devices are switched to the on condition, andthen in the subsequent period from the time point where the first linecurrent comparison result becomes of a first level up to a time-point ofthe next state update timing, the fourth switching power device isswitched to the off condition while the first switching power device isswitched to the on condition, and then in the subsequent period from thetime-point where the second line current comparison result (HV) becomesof a first level up to a time-point of the next state update timing, thefifth switching power device is switched to the off condition while thesecond switching power device is switched to the on condition; and atsaid state update timing, when the first line current comparison result(HU) is of a second level (iFU<iTU) and the second line currentcomparison result (HV) is of a first level (iFV>iTV) and the third linecurrent comparison result is of a first level (iFW>iTW), the first,fifth and sixth switching power devices are switched to the offcondition while the second, third and fourth switching power devices areswitched to the on condition, and then in the subsequent period from thetime-point where the second line current comparison result (HV) becomesof a second level up to a time-point of the next state update timing,the second switching power device is switched to the off condition whilethe fifth switching power device is switched to the on condition, andthen in the subsequent period from the time-point where the third linecurrent comparison result (HW) becomes of a second level up to atime-point of the next state update timing, the third switching powerdevice is switched to the off condition while the sixth switching powerdevice is switched to the on condition; and at said state update timing,when the first line current comparison result (HU) is of a first level(iFU>iTU) and the second line current comparison result (HV) is of asecond level (iFV<iTV) and the third line current comparison result (HW)is of a first level (iFW>iTW) , the second, fourth and sixth switchingpower devices are switched to the off condition while the first, thirdand fifth switching power devices are switched to the on condition, andthen in the subsequent period from the time-point where the first linecurrent comparison result (HU) becomes of a second level up to atime-point of the next state update timing, the first switching powerdevice is switched to the off condition while the fourth switching powerdevice is switched to the on condition, and then in the subsequentperiod from the time-point where the third line current comparisonresult (HW) becomes of a second level up to a time-point of the nextstate update timing, the third switching power device is switched to theoff condition while the sixth switching power device is switched to theon condition; and at said state update timing when the first linecurrent comparison result (HU) is of a first level (iFU>iTU) and thesecond line current comparison result (HV) is of a first level (iFV>iTV)and the third line current comparison result (HW) is of a second level(iFW<iTW), the third, fourth and fifth switching power devices areswitched to the off condition while the first, second and sixthswitching power devices are switched to the on condition, and then Inthe subsequent period from the time-point where the first line currentcomparison result (HU) becomes of a second level up to a time-point ofthe next state update timing, the first switching power device isswitched to the of condition while the fourth switching power device isswitched to the on condition, and then in the subsequent period from,the time-point where the second line current comparison result (HV)becomes of a second level up to a time-point of the next state updatetiming, the second switching power device is switched to the offcondition while the fifth switching power device is switched to the oncondition.
 4. The PWM converter as claimed in claim 2, wherein saidlogic circuit is adapted to determine the switching instruction signalssuch that,at said state update timing, when the first line currentcomparison result (HU) is of a first level (iFU>TU) and the second linecurrent comparison result (HV) is of a second level (iFV<iTV) and thethird line current comparison result (HW) is of a second level(iFW<iTW), the second, third and fourth switching power devices areswitched to the off condition while the first, fifth and sixth switchingpower devices are switched to the on condition, and when the second linecurrent comparison result (HV) becomes of a first level prior to thethird line current comparison result (HW), the fifth switching powerdevice is switched to the off condition while the second switching powerdevice is switched to the on condition which the conditions remain up toa time-point where the third line current comparison result (HW) becomesof a first level, and then in the subsequent period from the time-pointwhere the third line current comparison result (HW) becomes of a firstlevel up to a time-point of the next state update timing, the first,second and third switching power devices are switched to the offcondition while the fourth, fifth and sixth switching power devices areswitched to the on condition, whereas when the third line currentcomparison result (HW) becomes of a first level prior to the second linecurrent comparison result (HV), the sixth switching power device isswitched to the of condition while the third switching power device isswitched to the on condition which the conditions remains up to atime-point where the second line current comparison result (HV) becomesof a first level, and then in the subsequent period from the time-pointwhere the second line current comparison result (HV) becomes of a firstlevel up to a time-point of the next state update timing, the first,second and third switching power devices are switched to the offcondition while the fourth, fifth and sixth switching power devices areswitched to the on condition; and at said state update timing, when thefirst line current comparison result (HU) is of a second level (iFU<iTU)and the second line current comparison result (HV) is of a first level(iFV>iTV) and the third line current comparison result (HW) is of asecond level (iFW<iTW) , the first, third and fifth switching powerdevices are switched to the off condition while the second, fourth andsixth switching power devices are switched to the on condition, and whenthe third line current comparison result (HV) becomes of a first levelprior to the first line current comparison result (HU), the sixthswitching power device is switched to the off condition while the thirdswitching power device is switched to the on condition which theconditions remain up to a time-point where the first line currentcomparison result (HU) becomes of a first level, and then in thesubsequent period from the time-point where the first line currentcomparison result (HU) becomes of a first level up to a time-point ofthe next state update timing, the first, second and third switchingpower devices are switched to the off condition while the fourth, fifthand sixth switching power devices are switched to the on condition,whereas when the first line current comparison result (HU) becomes of afirst level prior to the third line current comparison result (HW), thefourth switching power device is switched to the on condition while thefirst switching power device is switched to the on condition which theconditions remain up to a time-point where the third line currentcomparison result (HW) becomes of a first level, and then in thesubsequent period from the time-point where the third line currentcomparison result (HW) becomes of a first level up to a time-point ofthe next state update timing, the first, second and third switchingpower devices are switched to the off condition while the fourth, fifthand sixth switching power devices are switched to the on condition; andat said state update timing, when the first line current comparisonresult (HU) is of a second level (iFU<iTU) and the second line currentcomparison result (HV) is of a second level (iFV<iTV) and the third linecurrent comparison result (HW) is of a first level (iFW>iTW), the first,second and sixth switching power devices are switched to the offcondition while the third, fourth and fifth switching power devices areswitched to the on condition, and when the first line current comparisonresult (HU) becomes of a first level prior to the second line currentcomparison result (HV), the fourth switching power device is switched tothe off condition while the first switching power device is switched tothe on condition which the conditions remain up to a time-point wherethe second line current comparison result (HV) becomes of a first level,and then in the subsequent period from the time-point where the secondline current comparison result (HV) becomes of a first level up to atime-point of the next state update timing, the first, second and thirdswitching power devices are switched to the off condition while thefourth, fifth and sixth switching power devices are switched to the oncondition, whereas when the second line current comparison result (HV)becomes of a first level prior to the first line current comparisonresult (HU), the fifth switching power device is switched to the offcondition while the second switching power device is switched to the oncondition which the conditions remain up to a time-point where the firstline current comparison result (HU) becomes of a first level, and thenin the subsequent period from the time-point where the first linecurrent comparison result (HU) becomes of a first level up to atime-point of the next state update timing, the first, second and thirdswitching power devices are switched to the off condition while thefourth, fifth and sixth switching power devices are switched to the oncondition; and at said state update timing, when the first line currentcomparison result (HU) is of a second level (iFU<iTU) and the secondline current comparison result (HV) is of a first level (iFV>iTV) andthe third line current comparison result (HW) is of a first level(iFW>iTW), the first, fifth and sixth switching power devices areswitched to the off condition while the second, third and fourthswitching power devices are switched to the on condition, and when thesecond line current comparison result (HV) becomes of a second levelprior to the third line current comparison result (HW), the secondswitching power device is switched to the off condition while the fifthswitching power device is switched to the on condition which theconditions remain up to a time-point where the third line currentcomparison result (HW) becomes of a second level, and then in thesubsequent period from the time-point where the third line currentcomparison result (HW) becomes of a second level up to a time-point ofthe next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition,whereas when the third line current comparison result (HW) becomes of asecond level prior to the second line current comparison result (HV),the third switching power device is switched to the off condition whilethe sixth switching power device is switched to the on condition whichthe conditions remain up to a time-point where the second line currentcomparison result (HV) becomes of a second level, and then in thesubsequent period from the time-point where the second line currentcomparison result (HV) becomes of a second level up to a time-point ofthe next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition; andsaid state update timing, when the first line current comparison result(HU) is of a first level (iFU>iTU) and the second line currentcomparison result (HV) is of a second level (iFV<iTV) and the third linecurrent comparison result (HW) is of a first level (iFW>iTW), thesecond, fourth and sixth switching power devices are switched to the offcondition while the first, third and fifth switching power devices areswitched to the on condition, and when the third line current comparisonresult (HW) becomes of a second level prior to the first line currentcomparison result (HU), the third switching power device is switched tothe off condition while the sixth switching power device is switched tothe on condition which the conditions remain up to a time-point wherethe first line current comparison result (HU) becomes of a second level,and then in the subsequent period from the time-point where the firstline current comparison result (HU) becomes of a second level up to atime-point of the next state update timing, the fourth, fifth and sixthswitching power devices are switched to the off condition while thefirst, second and third switching power devices are switched to the oncondition, whereas when the first line current comparison result (HU)becomes of a second level prior to the third line current comparisonresult (HW), the first switching power device is switched to the offcondition while the fourth switching power device is switched to the oncondition which the conditions remain up to a time-point where the thirdline current comparison result (HW) becomes of a second level, and thenin the subsequent period from the time-point where the third linecurrent comparison result (HW) becomes of a second level up to atime-point of the next state update timing, the fourth, fifth and sixthswitching power devices are switched to the off condition while thefirst, second and third switching power devices are switched to the oncondition; and at said state update timing, when the first line currentcomparison result (HU) is of a first level (iFU>iTU) and the second linecurrent comparison result (HV) is of a first level (iFV>iTV) and thethird line current comparison result (HW) is of a second level(iFW<iTW), the third, fourth and fifth switching power devices areswitched to the off condition while the first, second and sixthswitching power devices are switched to the on condition, and when thesecond line current comparison result (HV) becomes of a second levelprior to the first line current comparison result (HU), the secondswitching power device is switched to the off condition while the fifthswitching power device is switched to the on condition which theconditions remain up to a time-point when the first line currentcomparison result (HU) becomes of a second level, and then in thesubsequent period from the time-point where the first line currentcomparison result (HU) becomes of a second level up to a time-point ofthe next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition,whereas when the first line current comparison result (HU) becomes of asecond level prior to the second line current comparison result (HV),the first switching power device is switched to the off condition whilethe fourth switching power device is switched to the on condition whichthe conditions remain up to a time-point where the second line currentcomparison result (HV) becomes of a second level, and then in thesubsequent period from the time-point where the second line currentcomparison result (HV) becomes of a second level up to a time-point ofthe next state update timing, the fourth, fifth and sixth switchingpower devices are switched to the off condition while the first, secondand third switching power devices are switched to the on condition. 5.The FWM converter according to any one of claims 1 to 4, wherein thefirst, second and third comparators (17, 18, 19) are adapted toperiodically compare the first, second and third line currentinstruction values with the first, second and third line currentmeasurement results, respectively, and wherein said current controller(6) further comprises first, second and third double-reading logiccircuits (48, 49, 50) respectively interconnected between the first,second and third comparators (17, 18, 19) and the logic circuit (10)adapted such that, in the case where the first, second and third linecurrent measurement results are greater than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of a firstlevel, and whereas, in the case where the first, second and third linecurrent measurement results are smaller than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of asecond level, respectively.
 6. The PWM converter according to claim 5,wherein the logic circuit further includes first, second and third delayunits (56, 57, 58) for delaying switching instruction signals (PU, PV,PW) by predetermined times in accordance with a predetermined rule to befed to the main circuit power control section (8).
 7. The PWM converteraccording to claim 1, wherein the current instruction generator (7)generates the first, second and third line current instruction signals,each consisting of a sine wave of in-phase or a sine wave of anti-phasewith respect to each phase voltage, seen from the neutral point of thethree-phase AC power source.
 8. The PWM converter according to claim 3,wherein the first, second and third comparators (17, 18, 19) are adaptedto periodically compare the first, second and third line currentinstruction values with the first, second and third line currentmeasurement results, respectively, and wherein said current controller(6) further comprises first, second and third double-reading logiccircuits (48, 49, 50) respectively interconnected between the first,second and third comparators (17, 18, 19) and the logic circuit (10)adapted such that, in the case where the first, second and third linecurrent measurement results are greater than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of a firstlevel, and whereas, in the case where the first, second and third linecurrent measurement results are smaller than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of asecond level, respectively.
 9. The PWM converter according to claim 2,wherein the first, second and third comparators (17, 18, 19) are adaptedto periodically compare the first, second and third line currentinstruction values with the first, second and third line currentmeasurement results, respectively, and wherein said current controller(6) further comprises first, second and third double-reading logiccircuits (48, 49, 50) respectively interconnected between the first,second and third comparators (17, 18, 19) and the logic circuit (10)adapted such that, in the case where the first, second and third linecurrent measurement results are greater than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of a firstlevel, and whereas, in the case where the first, second and third linecurrent measurement results are smaller than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of asecond level, respectively.
 10. The PWM converter according to claim 2,wherein the first, second and third comparators (17, 18, 19) are adaptedto periodically compare the first, second and third line currentinstruction values with the first, second and third line currentmeasurement results, respectively, and wherein said current controller(6) further comprises first, second and third double-reading logiccircuits (48, 49, 50) respectively interconnected between the first,second and third comparators (17, 18, 19) and the logic circuit (10)adapted such that, in the case where the first, second and third linecurrent measurement results are greater than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of a firstlevel, and whereas, in the case where the first, second and third linecurrent measurement results are smaller than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of asecond level, respectively.
 11. The PWM converter according to claim 1,wherein the first, second and third comparators (17, 18, 19) are adaptedto periodically compare the first, second and third line currentinstruction values with the first, second and third line currentmeasurement results, respectively, and wherein said current controller(6) further comprises first, second and third double-reading logiccircuits (48, 49, 50) respectively interconnected between the first,second and third comparators (17, 18, 19) and the logic circuit (10)adapted such that, in the case where the first, second and third linecurrent measurement results are greater than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of a firstlevel, and whereas, in the case where the first, second and third linecurrent measurement results are smaller than the first, second and thirdline current instruction values at least successive two times,respectively, the first, second and third comparators output the first,second and third line current comparison results (HU, HV, HW) of asecond level, respectively.